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The phase-frequency detector (PFD) with a double-ended charge pump output driver was invented when the IC age arrived 40 years ago. The PFD quickly replaced the analog mixer to become the standard of phase-locked loop (PLL) applications due to its frequency-capturing ability with a single stable operating point. Despite its popularity, the PFD always produces an annoying dead-zone jittering glitch. For years, design engineers have learned to live with this glitch by pushing the operating point of the PFD away from the dead zone by adding more delay to the reset path of PFD to increase the size of the glitch. In doing so, the two signals to the PFD are always locked with a phase offset to produce an error signal to cancel out the glitch, and the PFD always outputs a constant pulse train to modulate the VCO. As a result, the phase noise of the VCO is high, the gain of the PFD is low, and the operating speed of the PFD is also slow.

The schematic of the PFD with a double-ended charge pump is shown in Figure 1, and its timing diagram is shown in Figure 2. The PFD is composed of two flip-flops and an AND gate. One of the flip-flops will be set when the early arrival signal arrives and both flip-flops will be reset after the late arrival signal arrives. The PFD is only a device to detect the arrival sequence between two signals. The operation of the PFD is made of two arrival events, one arrival event occurring at each of the two inputs. To function as a phase/frequency detector, this circuit includes a double-ended charge pump to produce an output that can be changed by the arrival-time difference between the signals applied to the inputs. However, it is appropriate to revisit the definition of a phase-frequency detector to determine whether the circuit in Figure 1 effectively meets these requirements.

If the PFD is a phase-frequency detector, it should be able to detect both the frequency error and phase error linearly. We can test whether the PFD is a frequency detector by simply supplying a fixed-frequency signal to the VCO input, F_VCO, of the PFD and supplying a variable frequency signal to the reference input, F_REF, of the PFD and connecting the output of the PFD to a low-pass filter. Because there will only be a pulse train from the current source associated with the higher-frequency signal, the low-pass filter (LPF) voltage will saturate to either the high- or low-voltage rail when the frequency difference is large. When the frequency difference is small, one of the currrent sources will be turned on more often than the other. Therefore, the PFD does function as a frequency detector.

To test whether the PFD is a true phase detector, a fixed-frequency signal can be supplied simultaneously to F_VCO and to a variable-delay circuit whose output feeds F_REF. This will produce a variable phase delay. With the output of the PFD connected to the LPF as before, the measured result shows that the PFD is not a true linear phase detector, because the output of the LPF can only stay at either the saturated high or low state, depending upon which signal has a phase lead over the other.

Based on this analysis, the PFD circuit is actually an arrival-time detector. We can prove this point by repeating the last test, but replacing the fixed-frequency signal with a one-shot generator. A one-shot generator produces only a single pulse with a single rising edge per triggering event, and the variable delay circuit allows for adjustment of the arrival-time difference between the VCO input and reference input signals. The output at the low-pass filter is found to be a linear voltage step proportional to the arrival-time difference between two input signals. The PFD is thus seen to be an arrival-time detector, instead of a phase-frequency detector, because it provides a steady-state output that provides both polarity and magnitude of the measured time difference. When we are comparing the frequency or phase between two periodic signals, the signals must be a continuous pulse train. However, only a single pulse is needed from each input signal when comparing the arrival times between them.

The glitch problem of the PFD with double-ended charge pump is inherent since the charge pumps will always be turned on at the end of the comparison cycle and the current output from two charge pumps will never be equal due to intrinsic noise. As a result, there is always an erroneous output when both input signals arrive at the PFD at the same time. To overcome this problem, engineers must add more delay to the reset path of the PFD to increase the width of the reset signal and to increase the size of the glitch. The two input signals now will never arrive at the same time in order to produce an error output signal that cancels out the error caused by the glitch. By inserting an intentional delay in the reset path, the PFD is operated away from the unstable zero-arrival-time-difference point and the unstable dead zone jittering is thus prevented. As a result, the basic PFD circuit in Figure 1 always produces two output spikes to modulate the VCO, one due to the glitch, and the other due to the intentionally inserted delay.

The advent of ASICs and FPGAs with standard cell structure during the 1980s brought changes to PFD design, since the double-ended charge pump output driver is not available in these devices. To overcome this difficulty, the PFD must be used with the tri-state output driver configured as a single-ended charge pump. Engineers were already so familiar with the dead zone jittering problem that they immediately knew what to do when the dead zone jittering problem appeared with the new design.

A schematic for a PFD driving a single-ended charge pump is shown in Figure 3, and its timing diagram is shown in Figure 4. The single-ended charge pump requires a separate polarity input (to select either sinking or sourcing the LPF current) and an enable input to either drive current or tri-state the output). The enable input signal determines the duration of the current pulse applied by the output to the LPF. Ideally, the single-ended charge pump driver's output should be biased such that the output is exactly half of Vcc, so that it produces equal positive and negative output currents.

Although the PFD with a single-ended charge pump still produces a glitch, the glitch is produced due to the delay mismatch between the enable signal and the polarity signal. Fortunately, this glitch only exists for the case when the leading edge of F_VCO occurs before that of F_REF, and is thus quite manageable. Furthermore, the PFD with a single-ended charge pump output shown in Figure 3 can still produce an error-free positive polarity output when the reference input signal arrives earlier. A complementary version of the same circuit can then produce an error-free negative polarity output when the VCO input signal arrives earlier. With a polarity selection circuit as shown in Figure 5, it is possible to produce a completely error-free polarity output signal for the tri-stating output driver acting as the charge pump.

The polarity selection circuit determines which of the two signals applied to their respective inputs was the first to arrive. This will either be the positive (or logic high) signal generated when F_REF leads F_VCO, or the negative (or logic low) signal generated when F_VCO leads F_REF.

During stable operation of the circuit, the first signal to arrive will generate a feedback signal to block the other signal to prevent it from changing the final polarity output that has been established by the first signal. Because it takes time to generate the feedback signals between gates, the feedback signal might not be able to block the other signal if the other signal arrives before the feedback signal has been generated. As a result, the late arrival signal will not be blocked completely when the arrival-time difference between the two input signals is less than a propagation delay of a single logic gate. This is not a problem when the flip-flop output signal generated by F_REF arrives at the polarity selection circuit earlier, since the signal generated by F_VCO will not be able to change the positive value on the final polarity output due to the electrical properties of the OR gate, even if the signal is not blocked completely. However, this signal created by F_VCO does create a problem when it arrives earlier, because the signal generated by F_REF can still change the final polarity output value from negative to positive when the arrival-time difference is less than the propagation delay time of a single logic gate. As a result, the final polarity output can bounce. The bouncing of final polarity output occurs only when the VCO flip-flop output signal arrives earlier than the reference flip-flop output signal by less than the propagation delay of a single logic gate, so that the decision threshold is shifted to favor the positive signal triggered by F_REF by the amount of half of the propagation delay of a single logic gate. Other than this slight shift of decision threshold, the design in Figure 5 is a nearly ideal arrival-time detector.

When the two input signals arrive within the decision threshold, the final polarity output signal from the polarity selection circuit will bounce between high and low logic levels with a 50% duty cycle so that the net output current supplied by the charge pump is always zero, and the decision threshold becomes a stable operating point. Due to this effect, the glitch problem is solved completely.

The enabling time of the single-ended charge pump output can be adjusted according to need. The enabling time can be made exactly equal to the arrival-time difference between the two input signals by using an exclusive OR gate, as shown in Figure 5. It can also be made slightly longer than the arrival-time difference by using the polarity output signal as the enable signal, thereby turning on the enable signal longer, as shown in Figure 6. When the enabling time is equal to the arrival-time difference, a dead zone is inevitable since the enabling time can be too short to overcome the input-gating threshold of the output driver when the arrival-time difference is small. However, since the duration of the polarity output signal of the PFD is always longer than the arrival-time difference by an amount equal to the reset time for one of the flip-flops, the polarity output signal is usually long enough not only to overcome the input-gating threshold of the output driver but also to overcome the slew-rate propagation delay of the output driver. As a result, the single-ended charge pump output driver can always produce a full-swing digital output, regardless of how small the arrival-time difference is when the polarity signals from the flip-flops are fed directly to the circuit that generates the final enable signal of the output driver. This full-swing capability ensures that the phase gain of the arrival-time detector is V_CC/2 at the output of the charge pump, significantly greater than that of the basic PFD circuit shown in Figure 1.

The output from the arrival-time detector shown in Figure 6 is a random, non-coherent wideband pulse train while the output generated from the traditional PFD is a coherent pulse train. Because a non-coherent random pulse train has a much lower power density than any coherent pulse train, the arrival-time detector generates significantly lower phase noise in the VCO than the traditional PFD.

The slight offset of the decision threshold in the Figure 6 circuit can be removed by using the design shown in Figure 7. In this design, the final polarity output from the second-stage OR gate in the polarity selection circuit is used to drive a sinking charge pump switch (active low) directly so that the sinking charge pump will never be turned on when the signal triggered by F_REF arrives first. The sinking charge pump will start to turn on when the signal triggered by F_VCO arrives first, and the bouncing decision will never produce an erroneous output since an erroneous decision will never enable the sinking charge pump. An AND gate produces the other final polarity output signal to drive the sourcing charge pump switch. Since the sourcing charge pump will never be turned on when the signal triggered by F_VCO arrives first, it can produce an output current only when the signal triggered by F_REF arrives earlier. As a result, the output current is always accurate, precise and virtually error-free, regardless of how small the arrival-time difference is between the leading edges of F_REF and F_VCO. The design shown in Figure 7 thus makes an ideal arrival-time detector.

Wen Lin is the president of Keystone Semiconductor. He started the company after he invented the arrival-time detector in early 2005. He has subsequently submitted five patent applications related to the arrival-time locked loop technology. Additionally, he has been a hardware engineer for 28 years. He graduated from National Taiwan University with a BSEE in 1978 and Penn State with an MSEE in 1984. His experiences ranged from dc to microwave frequencies, digital to analog/RF design, and circuit- to system-level electronics. He started Omnispread Communications in 1993 to design and produce spread-spectrum radio modems for the industry and he has been the president of OCI since then. He can be reached via e-mail at wlin@keystonesemiconductor.com.