VME board supplier Pentek Inc. has announced its first entry into the cPCI market with a 3U 16-channel multiband-receiver board and a 6U 32-channel multiband-receiver board featuring 14-bit analog-to-converters (ADCs) and Virtex-II FPGAs (field-programmable gate arrays) for signal processing. Both boards consist of one or two model 7131 digital receiver PMC modules and a PMC-to-cPCI adapter assembled and tested as a single cPCI board.

Both COTS (commercial-off-the-shelf) cPCI boards were designed to maximize configuration flexibility, switching and optimized synchronization for software radio applications such as synchronous data communications, wireless base stations, direction finding, satellite communications, wireless LAN, high-frequency sonar and telecommunications.

The model 7231 accepts four analog RF inputs at +4 dBm full scale into 50 Ω on front-panel SMA connectors, while the model 7331 offers two analog inputs. Each input is transformer-coupled and digitized by an AD6645 14-bit ADC with options for maximum sampling rates of either 80 MHz or 105 MHz. The sampling clock can be driven from an internal 80 MHz or 100 MHz crystal oscillator, from an external 50-Ohm clock source supplied to a front-panel SMA connector or from the front-panel LVDS clock/sync bus.

The ADC data are delivered to eight Graychip GC4016 quad multiband digital-receiver chips on the model 7231 or four quad receiver chips on the 7331. The maximum input sampling rate for the GC4016 is 100 MHz. Each GC4016 includes four receiver channels capable of independent center frequency tuning from DC to ƒS/2, where ƒS is the sample clock frequency. Additionally, ADC data can be delivered directly to the FPGAs, bypassing the digital receivers for wideband applications.

The front-panel LVDS clock/sync bus allows one board to act as a master, driving the sample clock, sync, gating and trigger signals through the LVDS clock/sync bus. This supports synchronization of local oscillator phase, frequency switching, decimating filter phase and data collection across multiple boards. When used with Pentek's model 9190 clock and sync generator, the boards can support up to 1,280 channels, each sharing a common clock and synchronization signals, for large multichannel systems including beamforming applications.

The 7231 and 7331 are both equipped with Xilinx Virtex-II FPGAs. Data from the ADC and from the GC4016 digital receivers are delivered into the FPGAs, which perform a wide range of user-selectable data packing and formatting functions. Dual port memories inside the FPGAs provide efficient PCI bus transfers by buffering receiver and ADC data.

By choosing either the Xilinx Virtex-II XC2V1000 (standard) or optional XC2V3000 FPGAs, users can implement complex DSP algorithms and take advantage of flexible custom I/O through the cPCI P3 and P5 connectors. Industry-standard 64-bit 66 MHz PLX9656 PCI interface chips ensure full conformance to all PCI bus timing specifications. A PCI bridge connects the two PCI interfaces to the cPCI backplane.

Pentek's three-fold GateFlow FPGA resources include the GateFlow FPGA Design Kit supporting user-developed FPGA code, GateFlow IP Core libraries for high-performance FFTs (Fast Fourier Transforms), digital receivers and radar pulse compression algorithms and the GateFlow Factory Installed IP cores.

Third-party and Pentek software development tools are available on Windows and Linux platforms. For more information, go to www.pentek.com.