It's no surprise that the mobile phone market is growing steadily — about 500 million mobile phones are in use worldwide. And, though the market is still primarily voice-based, additional services requiring broad bandwidths are gaining increased attention. As the popularity of these services grows, however, a number of hardware challenges exist in designing the baseband hardware for 3G terminals. Fortunately, there are also solutions.

In Japan, additional features such as banking, stock-exchange transactions, sports and weather information are offered through the i-mode, which grows by 50,000 subscribers every day. Short messaging service (SMS) is tremendously popular in Europe as well. The introduction of wireless application protocol (WAP) has boosted this evolution further, but it suffered from the too-low data rates offered over a traditional GSM network.

The recent introduction of general packet radio service (GPRS) is the necessary stepping stone to true cellular data applications with sufficient user comfort. The 2002 introduction of the universal mobile telecommunication system (UMTS) in Europe will mark the advent of multimedia services offered via cellular terminals. The UMTS standard will surpass global system for mobile communications (GSM) and its GPRS derivative by offering greater flexibility for different applications over one air interface. And it will use spectrum resources more efficiently.

Most telecom companies and market analysts anticipate that the evolution to a multimedia-driven mobile market will begin in 2002. On the other hand, the Third Generation Partnership Project (3GPP) and 3GPP2 standards are only now being finalized. As a consequence, 3G baseband component design houses and terminal manufacturers face short development times if they want to introduce their products to the market early.

3G technology is also more complex, both in air interface and in applications. For this reason, a 3G system on chip (SOC) will include more functionality than, say, a GSM baseband application-specific integrated circuit (ASIC). Therefore, the intellectual property (IP) building blocks — or cores — need to include much larger functional entities as compared to current practice. For instance, rather than numerically controlled oscillators (NCOs) or pulse-shaping filters, a complete wideband, code-division multiple access (W-CDMA) transceiver is considered a building block for a baseband SOC (see Figure 1).

Flexibility is required to enable engineers to cope with rapid changes in standards as well as to make the product useful across a range of applications and multiservice terminals. When a specific core is required for a particular application, the adopted design method allows fast customization.

Low power consumption is a basic requirement for hand-held devices. The core achieves this by making the right hardware and software trade-offs for the physical layer (see Figure 2), and by applying low-power design techniques in the circuitry implementation (see Figure 3).

Nowadays, GSM and GPRS baseband architectures are digital signal processor (DSP)-centric, i.e. the DSP core performs the source codec function and the larger part of the physical layer waveform processing. For the near future, powerful DSP cores clocked at several hundreds of megahertz will be available. But, given the 3G waveform complexity and the high data rates to be processed, only a small part of the baseband processing can be handled by such a processor core. In such architectures, most of the 3G baseband operations are still to be executed in hardware accelerators (co-processors). This leads to a bus traffic bottleneck, which also contributes significantly to the power consumption. Even with DSP cores optimized for ultra-low power consumption, the power consumption associated with the highly multiplexed data paths and the massive on-chip (or even off-chip) memory needs force visionary 3G chip manufacturers to do it differently.

A more interesting approach, which allows the baseband power consumption to be reduced by at least an order of magnitude, allocates a DSP, clocked at a lower speed (e.g. 13 MHz), for the GSM baseband transceiver implementation and 3G source codec functions. This approach uses primarily reconfigurable hardware for the UMTS/FDD L1 functionality. In this architecture, the ARM (DEFINE) subsystem on top in Figure 3 performs parameter downloading at boot time and run-time closing of slow loops (e.g. for parameterization of different fading algorithms). The advantages over the high-speed DSP core approach are clear: The flexible logic is clocked at moderate speeds (around 20 MHz), and all the registers and small, distributed memories are accessed on-chip. At the same time, a sufficient level of flexibility is provided at a reasonable additional gate count.

Low-power design techniques are also exploited on the circuit level. W-CDMA architectures are multi-rate by nature, hence different clock frequencies are applied in different parts of the transceiver. Moreover, multiple services imply multiple data rates, depending on the activation of the service in the terminal. Also, when a terminal is just roaming, a considerable part of the digital functions should be switched off completely. It is therefore advantageous to have clock frequencies that are self-adaptable as a function of the operational parameters (see Figure 3).

Communication between blocks is organized through a handshake protocol. Clocks are ticking only when data have to be transferred, and idle clock cycles do not occur.

Data integrity is secured through the handshaking with the strobe and acknowledge signals.

Advantages of this data flow control (DFC)-based intermodule communications include the self-adaptability for different data rates and parameter configurations, as well as the significant reduction of the load on the high-frequency clock nets. Moreover, idle blocks are automatically switched off, which simplifies the implementation of the power-down modes of the terminal. The good news is that the hardware overhead of the DFC blocks is negligible.

The concept here is based on a hardware approach for reaching the software radio goal: rather than using a high-speed DSP, programmable hardware is used. This particular subsystem is the master of the reconfiguration control and reconfigurability allows one to:

• reconfigure between UMTS/FDD and IS-95.

• select alternative algorithms for channel estimation, searcher and finger management, etc.

• select various interfaces for different radio front-end architectures.

• reconfigure L1 for multiple applications, and the support of multiple services on a single terminal.

• reconfigure for GPS, Galileo (the European navigation satellite system) and S-UMTS (the satellite extension of terrestrial UMTS).

• keep track of the standardization evolution.

When a specific 3G core is required for a particular application, the modular design facilitates customization of the generic solution in a short time frame. Furthermore, in line with the 3G road map, the extensions to UMTS/TDD and to CDMA2000-compliant transceiver modules will naturally evolve out of the current flexible architecture.

To realize the 3GPP standard, several auxiliary physical channels must be transmitted and received together with the information-carrying channels. Furthermore, the number of the information-carrying channel's dedicated physical data channels (DPDCH) can vary depending on the data rate and the number of services that run on the terminal. The latter is referred to as multicode transmission. For this purpose, the cores referred to feature a channel matrix in the transmit section and the demodulators to allow a flexible mapping of channels on the logic. The multicode transmission aspect and the flexibility requirements have also lead to a different Rake concept compared to traditional cellular CDMA receiver implementations.

Depending on the application, different environments, multipath characteristics and Doppler characteristics are encountered. In some cases, applications have to function in different circumstances (e.g. a mobile Web browser used indoors and on board a fast train), which means that cell search and channel correction algorithms need to be reconfigurable on-the-fly. The core's demodulator architecture features the necessary flexibility to support this, and the ARM subsystem is in charge of controlling it.

The core architecture also supports the processing of GPS and Galileo satellite signals. Many 3G applications will require accurate positioning in one form or another. For the sake of emergency assistance, a duplex operation (switching between UMTS mode and navigation mode) is sufficient. The ARM will control this reconfiguration and will also calculate the navigation solution out of the pseudo-range measurements from the core's receiver correlators. For applications requiring simultaneous communications and navigation, the modular design allows straightforward extension with extra tracking units and duplication of the front-end interface.

Given the aggressive time schedules previously discussed, speeding up the baseband ASIC development is on the wish lists of most 3G component and terminal developers. The support required is not on the algorithm development, but on evaluating and fine-tuning the chosen parameters, optimizing the core for particular applications and simulating the core in the context of the entire baseband SOC.

The race for the first 3G terminals has started. The development schedules are aggressive, and the challenges are different from what was required for 2G phone development. Time-to-market, low power consumption and functional flexibility are the main requirements for 3G. The IP core technology discussed here is alternative to one providing the 3G baseband ASIC design teams with the tools to reach these goals.

Lieven Philips has 11 years of experience in the semiconductor industry. Prior to founding Sirius Communications, Lieven worked as a Philips-resident (Eindhoven, the Netherlands) at the Advanced Software Development Group of IMEC. At IMEC, Lieven was project leader for the support of the Cathedral-1 DSP-Digest design team. He extended the IMEC ASIC CAD tools for the design, simulation and filter optimization of high-precision digital filters for audio and compact disc applications. He holds several patents on the functionality, implementation and design strategy of innovative CDMA circuits and has lectured as an invited speaker at the University of Leuven on wireless communication techniques. He obtained his EE degree, option microelectronics, from the Katholieke Universiteit Leuven. He performed his masters' thesis at Philips on the design of an 18-bit sigma delta converter for digital audio applications. He can be contacted at Sirius Communications NV Wingepark 51B-3110 Rotselaar Belgium. Tel.: +32 16 44 44 02 Fax.: +32 16 44 54 81 e-mail: philips@siriuscomm.com

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