CDMA2000 Design and Performance Requirements
Feb 1, 2005 12:00 PM By Bill Schofield and Brad Brannon
Various heterodyne solutions have continued to flourish through incarnations of transceiver designs, each generation adding new control loops or components to improve the architectures. While communications standards such as CDMA2000 provide challenging performance requirements, the trends are for deep cost reduction, highly integrated solutions and flexibility.
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To reduce the costs of code-division, multiple-access systems, circuit stages are being integrated or reduced wherever possible, with an eye toward digitizing as soon as possible. This has resulted in strong interest in architectures such as direct conversion for high-performance receivers.
Direct conversion offers simplicity and a minimum of components consisting of an RF gain stage, in-phase and quadrature (IQ) demodulator and digitizing circuitry. This technique, in use for user equipment, is still a few years away from the provider side. In the meantime, intermediate frequency (IF) sampling is the preferred architecture, offering a compromise between performance and cost.
In addition to lowering cost, another benefit of IF sampling is that it offers great flexibility. The two main categories of analog filters are a band filter and a Nyquist filter. The band filter selects the band of interest, and the Nyquist filter prevents aliasing in the following analog to digital converter (ADC).
Beyond this, filters are implemented digitally in digital downconverters (DDC), such as Analog Devices' AD6636. In addition to downconversion, a DDC also provides programmable channel filtering and other critical functions such as gain control and power estimation. Because DDCs are digital and fully programmable, they can be changed to meet the needs of the standards currently being received. Although this is software-selectable, the manufacturer determines these characteristics as part of the firmware that is installed during the assembly and test process. Because it can be determined during manufacturing, a single basic design may be used for several deployments, reducing the costs associated with inventory, assembly and test.
While IF sampling and direct conversion are often used to reduce direct and indirect product costs, they do not come without technical challenges. Most notable is that with fewer stages, the required gain and filtering must take place with fewer devices, resulting in the need for devices with a lower noise figure (NF) and higher third-order intercept point (IP3) performance. Fortunately, as the demands for performance have increased, semiconductor device performance has met the challenge and enabled the reduced topologies.
Looking at a multicarrier application in CDMA2000, the minimum performance is defined by a sensitivity of -117 dBm/ 1.25 MHz. In addition, narrowband signals 87 dB or larger must also be tolerated in some bands. This places the largest signal somewhere around -30 dBm. While these are minimum specifications, many receivers typically outperform these numbers by many decibels. Because many of these systems are multicarrier, the large signals cannot be allowed to desensitize the receiver to the smaller desired signals. Therefore, gain control must be minimal or absent. Therefore, it is desirable for a fixed gain to be used. As shown in Figure 1, the ADC is the last analog element in the chain. Given a full scale on the ADC of about +5 dBm, the maximum conversion gain can be estimated. If the largest signal at the antenna is -30 dBm and the ADC can only tolerate a +5 dBm signal, this limits the gain to 35 dB, maximum. Current, state-of-the-art devices can produce this gain with an NF of about 3 dB.
Is this enough gain? To determine the answer, it is necessary to ensure that the noise floor of the front end (everything up to the ADC) is greater than the input-referred noise floor of the ADC. The noise from the front end is
The noise floor of a typical 14-bit ADC, such as the AD9444, is
Because the front-end noise density is much higher than that of the ADC, the ADC will not significantly contribute to overall sensitivity of the receiver. However, if additional sensitivity is desired, either an automatic gain control can be used or the 8 dB margin can be reduced or a combination of the two.
As shown in Table 1, signal levels can be high. It is not uncommon for IF output levels to approach levels as high as +15 dBm to overcome the loss of following analog filters such as the Nyquist filter shown in the example. Because these levels are so high, third-order intercepts can become a problem. In traditional receiver architectures this problem can be mitigated by distributing the gains and losses over more stages, but in a multicarrier IF sampling and direct conversion radio, this is often not possible. For a case in point, the Nyquist filter is often implemented as a surface-acoustic wave (SAW) filter. Because SAW filters have such high losses, their input levels must often be driven hard to overcome their loss. If the filter were a lower loss version, the input drive level could be greatly reduced and IP3 performance would be easier to meet.
Noted in Table 1 is the fact that the signal-to-noise ratio (SNR) of the desired signal (expressed in energy density) is about -16 dB. Because CDMA2000 uses correlation to detect the signal of interest, negative SNRs are acceptable as long as the correlation gain is high enough. For CDMA2000, the correlation gain is about 21 dB, resulting in an effective SNR of +5 dB for this example.
The transmit side poses even more challenges. Because of regulatory requirements and specifications found in the standards, complex feed forward and/or feedback loops must be used. Architectures become driven not only by costs, but by specifications such as code domain power, r/error vector magnitude and adjacent-channel power ratio. The standard for CDMA2000 (Section 4 of 3GPP2 C.S0010-B) defines a nominal test model having a pilot, sync, single paging channel and six traffic channels. Code-domain power (CDP) can be considered code-domain noise; if there is too much then the receiver's ability to de-correlate channels is reduced. For an SR1/RC3 carrier, the code-domain power shall be less than 27 dB. CDP can be calculated using error vector magnitude (EVM) and spreading factor (Walsh code).
Antenna power amplifiers' operating points are set so that signal crests are below the amplifier's maximum unsaturated output power. Depending on the type of information being transferred, a carrier can have high peak-to-average ratios (PAR) if the component signals add in-phase; combining multiple carriers further increases the probability of phase alignment, increasing the PAR. The increased PAR lowers the efficiency of the power amplifier for a fixed linearity. A single nominal test model carrier has 9.6 dB PAR for a 10
For greater efficiency, digital pre-distortion PA linearization moves the PA into saturation while compensating for the resulting distortion. Third-order intermodulation products in the forward path of a PA linearization loop will occupy a bandwidth three times that of the signal, centered on the signal, with fifth order occupying five times the signal bandwidth. The digital-to-analog converter (DAC) must have the same bandwidth to cancel the distortion. For six adjacent carriers, 37.5 MHz is needed for fifth-order cancellation. In the observation path, the RF is down-mixed and digitized to baseband where it is averaged with a digital signal processor, which also computes new pre-distortion coefficients. One possible digitization approach mixes down close to dc using an ADC nyquist bandwidth equal to the distortion bandwidth. For six adjacent carriers, a 92.16 MSps ADC is sufficient (Figure 2a). Alternatively, a down-mix to a low IF followed by an undersampling ADC captures the third-order components without aliasing with higher orders aliasing in band; for an IF of 76.8 MHz, a 61.44 MSps converter is sufficient (Figure 2b). The ADC's distortion should be lower than the desired antenna distortion, typically ≤70 dBc spurious-free dynamic range. The samples are averaged so the ADC's noise can be relaxed to -135 dBm/Hz, which is about 60 dB SNR. Literature suggests that digital pre-distortion and PAPR can improve the PA's effective IP3 by +15 dBm.
Within three times the signal bandwidth, the ACPR at a frequency offset, F
Using the above observations and equation, one can refer multicarrier linearity specifications to a single carrier and calculate signal chain requirements.
The 3GPP2 specification defines the waveform quality, r, using a single pilot channel and requires it be >0.912. Composite r is a better measure of system modulation accuracy, and if determined by component linearity, the below equation provides a good approximation.
The above approximation links to EVM by,
which can be used to approximate the CDP, as detailed above.
The 3GPP2 emissions requirements determine linearity, wideband noise and dynamic range requirements of the converters. To illustrate the requirements, a worked example of a 30 W PA, using PAPR and pre-distortion linearization for six carriers at an RF of greater than 1 GHz with category A emission requirements will be considered.
Consider first the linearity requirements for a single carrier (Figure 4a). The first requirement is -45 dBc/30 kHz from 885 kHz to 1.25 MHz. The second is a -45 dBc/30 kHz requirement at 1.25 MHz offset or -9 dBm/30 kHz, whichever is the more stringent. The next limitation is at 1.98 MHz, but since a single carrier's third-order distortion does not occupy 1.98 MHz, the defining limitation on a single carrier's linearity, for a 44.77 dBm/1.2288 MHz carrier, is the -9 dBm/30 kHz requirement. For six carriers (Figure 4b), per-carrier power is now 36.99 dBm/1.2288 MHz, occupying a distortion bandwidth of 7.479 MHz from the edge of the outermost carriers. The -9 dBm/30 kHz at 1.25 MHz is a requirement for multicarrier, but this does not define the linearity. A requirement starting at 2.25 MHz offset of -13 dBm/1 MHz defines the linearity requirement. With 3 dB margin over the specification, the ACPR requirement becomes -68.21 dBc/30 kHz at 2.25 MHz offset. Referring back to the single carrier case, (Figure 4c) dividing the frequency offset from the edge of the carrier by six gives a linearity requirement of -68.21 dBc/30 kHz at 887 kHz frequency offset. This is a harder linearity requirement than the single carrier case.
Consider the noise requirements. The single carrier case, Figure 5a, has a 9.67 dB peak-to-average ratio with 2.5 dB reduction for peak-to-average power reduction and 3 dB extra dynamic range for digital pre-distortion, giving a peak of 54.94 dBm/1.2288 MHz. Category A emission limits the noise to -13 dBm/1 MHz at a 4 MHz offset. With 3 dB of margin, this requires 70 dB of dynamic range or -130.94 dB/Hz noise power spectral density. The six-carrier case, Figure 5b, has 12.9 dB of peak-to-average ratio, but this can be reduced by 6 dB with peak-to-average power reduction. Allowing 3 dB extra dynamic range for digital pre-distortion puts the peaks at 54.67 dBm/1.2288 MHz, about the same as the single carrier peak.
The six-carrier requirement of -16 dBm/1MHz at 2.25 MHz offset determines the linearity. The wideband noise is defined by the -16 dBm/1 MHz category A emissions plus margin requirement. Looking at a simplified signal chain (Figure 6), modulators typically have an output power of -15 dBm. With 20 dB variable gain amplifier (VGA) gain, the PA needs 40 dB to deliver +45 dBm from the DAC. With PA linearization, a +15 dBm PA output third-order intercept point (OIP3) improvement can result. Modulators typically have an OIP3 of approximately +18 dBm, and VGAs have OIP3s exceeding +20 dBm for 20 dB gain. The cascaded OIP3 at the PA output is +75.15 dBm and suggests that the overall OIP3 is dominated by the PA and is insensitive to DAC linearity. This OIP3 gives -15.22 dBm/1 MHz at 2.25 MHz offset.
The modulator will typically have a noise contribution of about -155 dBm/Hz. Setting the DAC and synthesizer contributions to -155 dBm/Hz and -152 dBm/Hz, respectively, means that to achieve the wideband noise requirement of -16 dBm/1 MHz, with this gain planning, requires the VGA and PA to have an NF of 8 dB. With this level plan, the DAC's mean output is at -15 dBm. With 10 dB due to peak-to-average overhead, this puts the DAC's full scale output at -5 dBm. The DAC's dynamic range needs to be -150 dBFS/Hz. The AD9779 is suited to this signal chain. An approximate r of 0.9987 and a code domain power of -46.96 dB will result.
The requirements for high rate packet data access, 1x Evolution-Data Only (1×EV-DO), are detailed in the 3GPP2 specification C.S0032-0. The limitations on emissions are the same as discussed in this document, but the waveform quality factor, r, is improved to 0.97. So the system has to be more linear with similar noise requirements. As shown by the simplified signal chain design, the linearity is dominated by the PA and will have minimal impact on the converter performance requirements.
ABOUT THE AUTHORS
Bill Schofield is a senior staff design engineer with Analog Devices' High Speed Converter group in Wilmington, Mass. He has been designing converters for communications applications for 12 years, is a regular contributor to trade conferences and journals and holds more than 12 converter-related patents.
Brad Brannon is a systems applications engineer with Analog Devices' High Speed Converter Group in Greensboro, N.C. He has been with ADI for 21 years and has contributed to a number of articles on radio architectures and converter applications issues.
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