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Radio frequency (RF) ICs continue to benefit from advances in CMOS process technologies. Over the years, we have seen monolithic CMOS transceiver chips handling wider bandwidths to address the needs of cellular handsets. And packing more on-chip to offer system-on-a-chip (SoC) solutions for a variety of cellular and wireless bands. In reality, CMOS RF SoC chips are incorporating all the radio building blocks including the power amplifier, phase-locked loop (PLL) filter, and the antenna switch. Thus, CMOS continues to make strong inroads into the microwave territory, going well beyond 5 GHz. Now, the availability of unlicensed bands around 7 GHz and 60 GHz is motivating designers to make a giant leap and migrate deeper into this turf. These bands are intended to facilitate emerging applications like point-to-point wireless LANs, broadband Internet access, as well as automotive applications like short- (24 GHz) and long-range (77 GHz) radars for collision avoidance.

Operation in these frequency bands was once the exclusive domain of III-V-compound semiconductors, such as gallium arsenide (GaAs) and indium phosphide (InP). However, aggressive scaling and corresponding improvements in CMOS and silicon germanium (SiGe) technologies is making history. What may have been considered unthinkable a decade ago is now becoming a reality. And that was demonstrated at this month's IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, Calif. Researchers from around the world convened here to show that the CMOS and BiCMOS trend in millimeter wave ICs is real.

For the first time, scientists from National Taiwan University described two essential building blocks — a voltage-controlled oscillator and a broadband amplifier — for creating a robust 60 GHz radio in a conventional CMOS technology. In fact, this 0.13 µm-based push-push VCO is designed to cover a band of 110 GHz to 170 GHz. At 114 GHz out signal, it features a phase noise of -107.6 dBc/Hz at 10 MHz offset and power consumption of only 8.4 mW. Likewise, the broadband-cascaded multistage distributed amplifier was implemented in standard 90 nm CMOS technology. It achieves better than 7 dB gain with a bandwidth of 70 GHz, 10 dBm output power for 1dB compression at 30 GHz, 9.3 dBm IIP3 at 40 GHz and 6.4 dB average NF from 1 GHz to 25 GHz.

Similarly, researchers from UCLA displayed a 60 GHz direct-conversion CMOS receiver in 0.13µm CMOS consuming 9 mW from a 1.2 V supply. It provides a voltage gain of 28 dB with a noise figure of 12.5 dB. This direct-conversion receiver incorporates folded microstrip lines to create resonance at 60 GHz in a common-gate low-noise amplifier and active mixers.

Toward that goal, researchers from California Institute of Technology in Pasadena, Calif. showed that to support 500 Mbps QPSK signal with bandwidth in excess of 400 MHz, a 24 GHz phased-array transmitter could be built in 0.18 µm CMOS. In essence, the California Institute developers presented a fully integrated four-element phased-array transmitter at 24 GHz with on-chip power amplifiers. It has a beam-forming resolution of 10°, a peak-to-null ratio of 23 dB, and isolation between paths of 28dB. Each CMOS PA can deliver up to +14 dBm into a 50 Ω load.

For 60 GHz wireless applications, researchers from Germany's IHP disclosed a BiCMOS PLL with a lock range of 53.3 GHz to 55.7 GHz. It operates from a 3 V supply except for a first divide-by-two stage, which requires a 5 V supply. Total power consumption is 895 mW. In a joint paper by University of Toronto, Canada, Delft University of Technology, The Netherlands and IBM, the developers demonstrated a three-stage 21 GHz to 26 GHz SiGe BiCMOS power amplfier with 21 dBm output power. The PAE at 24 GHz is shown to be greater than 12.5%.

These presentations indicate that CMOS will continue its march into the microwave and millimeter wave turf slowly but steadily. And, the performance will only get better with time. However, for critical functions, it will depend on SiGe technology.