The ultimate goal of the wireless industry is to give everyone an inexpensive and reliable means of communications anywhere, anytime and to anyone. The pursuit of this goal and operation in a highly dynamic and competitive environment, challenges handset manufacturers with continuous expectations to offer phones with increased functionality and performance levels. It also challenges manufacturers to reduce size and weight and to increase talk times.

Also, the emerging new cellular standards predicate the demand for multimode, multiband sets with ever-increasing complexity. The designers are tasked with meeting these requirements, while simultaneously reducing cost and time-to-market.

In that vein, one of the enabling factors for achieving the leading edge in this competitive environment is the use of cheaper components with extended degrees of integration in all stages of signal processing — RF/IF, baseband and digital.

The level of component integration used in different sections of the GSM mobile sets is still divergent. Currently, the highest level is achieved in the baseband (BB) section. Typically, the handsets contain two BB ICs (excluding the discrete memory chip): a BB processor and an application-specific analog interface. In the RF/IF path, however, the situation is not the same.

Today, there are a number of different transceiver IC architectures. They typically combine the components of the receiver chain with local and transmitter frequency VCOs, synthesizers, analog PLL loops, IQ modulation/demodulation and power control loops.

The next generation of highly integrated ICs, which combine all of these functions, is beginning to appear on the horizon. The advantages of this higher level of integration, however, are not as explored in the transmitter chain and in the implementation of the front-end functions. The dual-band GSM handsets still contain, as separate components, the power amplifier (RFIC module), the front-end module (combining the diplexer and Tx/Rx switches), directional couplers and the power detector.

Two scenarios are foreseen for the evolution of the dual- or triple-band GSM architecture. This evolution depends on the device and on which core might be chosen for future integration of the front-end and transmitter functions of this future GSM architecture

The first one is based on the expansion of the switchplexer's functionality. This is done by incorporating the Rx SAW filters⁷, and eventually the directional couplers, in the module. The switchplexer modules are miniature, high-performance units, built on sophisticated low-temperature co-fired ceramic (LTCC) substrates. These modules are constructed of more than 10 dielectric layers with differing thickness. The implementation of the additional functions is relatively straightforward, but including these functions would increase the size of the module, and could have a negative impact on the net cost benefit.

The other evolutionary track revolves around the PA module and increases gain functionality. The integration of the power control components (directional couplers, detectors and controller IC) in the PA module significantly simplifies the design of the power-control loop. One force working against this integration is that the functions of the power controller IC have already been included in other ICs, so the direct cost benefits are not obvious. Also, the handset makers have to be convinced that they do not need the ability to tune the control loop anymore. The same holds for the integration of the transmit VCOs in the PA. These functions will be increasingly integrated in the transceiver ICs as they develop.

Another advantageous integration step, starting with the PA, is the implementation of the switchplexer's functions. The accomplishment of this step presents a significant engineering challenge because it has to make use of the much simpler substrate of the PA. The consecutive steps in these two integration concepts are shown in Figure 1.

The unit discussed in this article is a prototype of the first member of a PA/FE module family that offers a significant increase in functionality. The module is intended to replace almost all of the building blocks used in the traditional dual-band GSM transmitters' architectures: PA, low-pass filters, and directional couplers, as well as power detectors and the switchplexer. It could be used with custom-designed and off-of-the-shelf transceivers and power controllers.

The objectives pursued with this developmental concept, grouped by category, include:

• Functionality — power amplification, multiplexing of extended global system for mobile communications (EGSM) and digital communications systems (DCS) frequency bands, Tx/Rx switching and monitoring of the output power level.

• Price — clearly competitive to the combination of a GSM/DCS PA, coupler + detector and switchplexer module.

• Performance — equal to the performance level offered by “state-of-the-art,” separate front-end and Si PA modules.

• Size — 13.75 × 11mm (~150 mm²), land grid array second-level interconnect technology, plastic cap.

• Ease-of-use — self-contained (none, or a significantly limited number of components on the main PCB). No external tuning required.

  To meet these cost objectives, the accepted set of technologies for this development was limited to technologies, presently used in the standard PA modules:

• MOBi3 technology (a double poly-silicon bipolar technology with f_T = 25 GHz, f_max = 40 GHz and breakdown V_CE0 >5.5 VDC) for implementing the active devices, the driver RFICs and output transistors.

• Two complementary passive integration and interconnection technologies: LTCC and passive integration on high ohmic (>3kΩ/cm) silicon substrate. The LTCC substrate consists of five dielectric layers (ε_r=9.5) with total thickness of 550 μm and C_u metalization.

• PIN diode dies for switching elements in the Tx/Rx switches.

The module based on this design consists of two power amplifier line-ups and a front-end circuit (Figure 2). The amplifiers are biased (V_supply,nom = 3.5 VDC) through separate input pins, but they share common control signals: V_BAND and V_APC. The foremost is a logical one, which enables the selected line-up. The low level (below 0.7 VDC) activates the 900 MHz amplifier. A V_BAND level above 1.7 VDC selects the 1800 MHz line-up. The V_APC signal (0.2 - 2.2 VDC) controls the gain, and, respectively, the output power level of the active amplifier. In both PA line-ups, circuits are provided for monitoring the output power level. These circuits produce current signals, which are proportional to the actual collector current of the final stages of both line-ups and, consequently, to the output power. Those circuits use a DC bias separated from the PA's supply voltage.

The FE part, which occupies ~40 mm² of the substrate, is constituted of two PIN-diodes SP2T switches and a diplexer. Two control signals select between the Rx and Tx states of the switches. In the high state of the control signals (2.8 VDC), the Tx states are active, and the consumed currents are about 9 mA.

The two power amplifier line-ups have identical configurations. They include a driving RFIC, a single-ended last stage and an output-matching circuit implemented on a passive silicon die. The RFICs contain two RF stages, a part of the interstage matching circuit and biasing networks, which settle the quiescent currents of all RF transistors in function of V_APC voltage. The design of a similar RFIC is described in more detail in². The IC designs used in this module include additional band switches, used to enable the V_APC signal in the amplifier selected by V_BAND.

The interstage matching circuits between the RFICs and the final stages are implemented with discrete capacitors and inductors integrated in the LTCC substrate. To increase the overall gain of the DCS line-up, a prematching metal-oxide semiconductor (MOS) capacitor is used³.

On both of the output power amplifier device (PAD) dies, circuits for sensing the collector currents are implemented. They consist of single transistor cells, connected in current mirror configuration to the rest of the PADs. Additional networks for RF decoupling and inverting the slope of the detected current are also included. The slope inverter allows the current, delivered by the mirror transistor, to be pushed in a load connected to the ground. Therefore, the voltage developed on the load will be proportional to the PAD's collector current and, respectively, to the output power. The module is compatible with the power controllers designed for use with diode detectors.

The ratio between the emitter areas of the mirror transistors and the PADs are chosen in such a way that the currents are in the same range: ~0.5 mA to 10 mA for the GSM and DCS channels. In the operating range of the output power, the sensitivity of the power detectors varies from 30 to 200 μA/dB. At the lower power level (-5 to 5 dBm), at which the power control loop also has to be operational, the sensitivity is still higher than 10 μA/dBm.

Good thermal coupling between the mirror and the RF transistors contributes to the stability of the detector's performance over temperature (Figure 3a). Another important parameter — the dependence of the detected signal on the PA's supply voltage — is shown in Figure 3b.

All of the capacitors, and most of the inductors, integrated in the output-matching networks of the PAs are integrated on the passive silicon dies. This approach provides significant savings on the occupied substrate area and also increases the accuracy and repeatability of the integrated components. The matching circuits are designed to suppress the second and third harmonics to a level lower than -50 dBc. In combination with the switchplexer, the simulated harmonics levels were less than -75 dBc for GSM and -70 dBc for the DCS band. This allowed avoidance of separate low-pass filters and a decrease of the insertion loss in the Tx channels of the front end by 0.2 dB (The module transmitter characteristics, output power and efficiency, are shown on Figure 4 and Figure 5, respectively, for GSM and DCS bands).

Several front-end architectures have been evaluated, not only in terms of performance — insertion loss, isolation between the channels and harmonics suppression — but also in the production yield and sensitivity to components and processes spread.

Most of the attention has been paid to two diplexer structures: one consisting of simple low- and high-pass filters, the other incorporating a combination of different low-pass and stop-band filters in the GSM branch and high-pass and stop-band filters in the DCS branch^4,5. Although the second type is superior in some of the mentioned parameters, the use of the simple low-pass/high-pass design has been chosen. This choice proved to be more tolerant to the inaccuracy of the LTCC process, used as an integration technology for the entire diplexer circuit. Both of the Tx/Rx switches are built up according to the conventional scheme consisting of a series and a shunt PIN diodes separated by a λ/4 line.

The major challenges faced in the implementation of the chosen FE architecture (see Figure 6) were related to the composition of the LTCC system. In this case, only five dielectric layers had uniform permeability and almost constant thickness. This LTCC substrate is not well-suited for integration of capacitors, nor is it suitable for implementation of real three-dimensional RF structures using multiple 50Ω transmission lines located on different layers and shielded with ground planes.

The first problem — integration of capacitors — was especially important for the design of the series capacitors, constituting the high-pass filter in the DCS branch of the diplexer. To preserve the proper high-pass response, a major requirement is to keep the value of their parasitic capacitance to ground minimal. A conventional design of a series plate capacitor, integrated in the used LTCC substrate at a maximal distance from the ground plane, would have at least 20% shunt capacitance.

A significant improvement of the DCS-band performance of the diplexer has been achieved by minimizing the parasitic capacitances and the length of the interconnects. This results in a broadband, low-loss performance of the DCS channels.

The second limitation, originated from the attributes of the used LTCC substrate, is the useful range of characteristic impedances (Z₀), feasible with stripline transmission lines. The highest impedance, achievable with stripline with maximally distant ground planes and minimal allowed (100 μm) width of the inner conductor, is about 45Ω. The investigation of the loss mechanisms in the used LTCC technology⁶ has shown that the cross-section of narrow strips (less than 200 μm) is rhomboidal, rather than rectangular, which decreases the effective RF conductivity and causes relatively high losses in the narrow striplines.

To overcome this problem, the approach has been to minimize the losses by implementing the λ/4 transmission lines with lower characteristic impedance and simultaneously obtain good impedance matching of the Rx channels.

The PIN-diode dies used offer a good compromise between low off-capacitance (C_OFF <0.3 pF) and reasonable on-resistance (R_ON <2Ω). The necessary performance of these PIN diodes has been obtained by mounting them as a naked die to avoid the parasitic capacitance's increase of diode packaging. The same diodes have been used both for series and shunt applications.

Usually, a resonant circuit, parallel to the series diodes, is used to increase the isolation of the diodes in series switches. The use of the high-performance bare PIN diodes made it possible to implement a simpler switch design that doesn't need such resonant circuits to obtain sufficient isolation.

The receiver characteristics of the FE are shown on Figure 7 and Figure 8, respectively, for GSM and DCS bands.

The major transmit and receive characteristics of the module are presented in Table 1 (page 36). The table includes the averaged parameters of both commercially available double-band, LTCC FE modules, as well as the ones described in this design. The comparison shows that the proposed PA + FE design has been successfully adopted to the simple LTCC system and, as a result, the performance level of the Rx channels of the combined PA plus FE module is comparable to the stand-alone FE modules.

The overall performance of the Tx channels is already comparable to the combination of the specification figures of separate state-of-the-art PA and FE. It's important to realize, however, that in a practical situation with a separate PA and FE, significant additional losses can also occur due to the coupler, which has to be included for power detection. The matching between PA, coupler and FE can also cause significant mismatch losses and will require major engineering efforts.

The harmonics suppression in the DCS band of this prototype is not yet sufficient, but can be easily optimized.

The design discussed in this paper proves the feasibility of the concept for further increase of the integration level in GSM front ends by implementing functionality in the PA module that was typically accomplished by stand-alone switchplexers and directional coupler/power detector units. The unit is completely self-contained and requires no external tuning or additional components.

Several paths are possible for the future evolution of this concept.

The first one is toward further miniaturization, maintaining the already-achieved functionality. The small number of the discrete components (four PIN diodes, two SMD inductors, two resistors and six capacitors) used in the FE circuit is a good precondition for reduction of the area occupied by the FE substrate area to about 25 to 30 mm². Reduction of the whole module dimensions to less than 100 mm² is also achievable.

A second possible evolutionary path is integration of the power controller IC in the module.

A third possible path is the integration of the RF SAW/BAW filters of the receiver paths. There is potential to simplify the construction of the switches and significantly increase the overall performance of the Rx channels. This, however, depends on advances and new concepts in SAW/BAW filters⁷.

For instance, maintaining the existing SP2T configuration of the DCS switch and connecting its Rx output to a SAW/BAW diplexer (which discriminates between the DCS and PCS Rx frequencies) will modify the current dual-band, front-end architecture to a triple-band solution.

Considering these evolutionary scenarios provide an interesting angle for considering the potential and the flexibility of the front-end integration approach used in the discussed module design.

1. N.J. Pulsford, J.T.M. van Beek, M.H.W.M. van Delden, A. Boogaard, “Passive integration on Si for RF circuits in wireless applications,” IEEE MTT-S Digest, 1999.

2. H.A. Visser, R. van der Last, T. Fric, R. Breunisse, A. Akhnoukh, “A fully integrated Si bipolar RF power amplifier for GSM operating from a single 3 volt supply voltage,” Proc. 28th Euro. Micro. Conf, pp. 656, Amsterdam 1988.

3. J. Sluijter, “Gain by prematching - a theoretical analysis,” July 1997 (Internal Philips report)

4. A. de Graauw, C. Copeti, W. Weekamp, “A new thin film passive integration technology for miniaturization of mobile phone front end modules,” IEEE MTT-S Digest, pp.1925-28, 2000.

5. T. Watanabe, K. Furutani, N. Nakajiama, H. Mandai, “Antenna switch duplexer for dual band phone (GSM/DCS) using LTCC multilayer Technology,” IEEE MTT-S Digest, pp. 215-18, 1999.

6. M. Kammerer, “Loss analysis for multilayer modules in LTCC and laminate technology”, 2001 (Internal Philips report).

7. M. Hikita, N. Matsuura, N. Shibagaki, and K. Sakiyama, “RF-circuit configurations and new SAW duplexers for single- and dual-band cellular radios,” IEEE MTT-S Digest, 1999.

Atanas Pentchev is a member of the technical staff with Philips Semiconductors in Nijmegen, The Netherlands, where he is working on the development of power-amplifier modules for mobile sets. He graduated from Budapest Technical University in 1983. Pentchev has more than 15 years of radio engineering experience in the development of military and consumer electronic equipment. His professional interests focus in design of on-system and device-level of transceivers intended for use in radars, point-to-point radios, satellite and mobile terminals. He can be reached at:
Atanas.Pentchev@Philips.com

Paul Swinkels is the development manager for power-amplifier modules at Philips Semiconductors in Nijmegen. He has worked as an IC designer, project manager and marketing manager with Philips Semiconductors since 1986. He received his masters degree in electrical engineering from the Eindhoven Technical University, the Netherlands in 1986. He can be reached at:
Paul.Swinkels@Philips.com

Guido Paola is development engineer at Philips Semiconductors in Nijmegen. He works with power amplifier modules and front-end integration. He received his masters degree in electrical engineering from the University of Catania, Italy in 2000. He can be reached at:
Guido.Paola@Philips.com

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