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Deployment of 2.5G and 3G wireless networks can now be accelerated with an innovative new test equipment architecture — one that enables spectral recording and playback of next-generation communications networks. Through the integration of gigabytes of high-speed memory with highly linear analog-to-digital (A/D), digital-to-analog (D/A), and RF up/down converters, the functionality of real-time RF signal acquisition is combined with direct-to-IF signal generation.

This is made possible by the ability of next-generation test instruments to capture field recordings of RF signals and play them back in the lab. This enables debugging of the system in the presence of real-world fading, interferers and adjacent channels — something that hasn't always been possible, or practical.

In addition, the RF record/playback capability permits capture of the output from prototype transmitters, which can be recreated via the RF signal generation capability. These prototype/proprietary format recordings can be distributed to the development team, enabling concurrent work on successive modules such as amplifiers and linearization circuits.

This unique platform tests pre-distortion algorithms and circuits for next-generation power amplifiers. Its core is the direct-to-IF approach.

Digital pre-distortion is considered the dominant technique for increasing efficiency and reducing cost in the latest 3G power amplifiers. Using this technique, designers can sample the RF output of their power amplifier and down-convert the signal to an IF. A/D converters digitize the IF, and digital signal processor (DSP) circuits implement algorithms to adjust the pre-distortion based on the detected output of the amplifier. Additional parameters affect the digital in-phase and quadrature (I/Q), as well as clipping circuits and lookup tables. These processing chains are used to adjust the digital I/Q stream prior to modulation, analog conversion and RF up-conversion. The goal is to increase power efficiency while keeping the adjacent channel power (ACP) leakage and error vector magnitude to a minimum. The block diagram in Figure 1 illustrates such a signal chain.

The bandwidths of pre-distortion circuits are typically three times the bandwidth of the output channel. This excess bandwidth allows detection and processing of the fundamental, in addition to the distortion products above and below the transmit channel. New instruments that have high output bandwidths (60 MHz and up) are able to accommodate testing of 3G multi-carrier power amplifiers used for universal mobile telecommunications service (UMTS/3GPP) applications; 20 MHz of transmit bandwidth for the four carriers at 5 MHz offset, and 20 MHz each for the upper and lower distortion products.

In an actual deployment, the entire chain illustrated in Figure 1 would be implemented in the power amplifier or digital radio sections of the base station. To assist designers in testing and verifying the algorithms, these wide-bandwidth vector signal generators can be used to simulate portions of the block diagram. Figure 1 indicates the test points in a typical pre-distortion signal chain. Annotations on this diagram illustrate the areas where the instruments can be used to simulate the digital, analog and RF sections of the pre-distortion circuit. Figure 2 shows a block diagram where such points exist.

This 3G equipment closely mimics sections of the signal chain being considered for the pre-distortion circuit. Inserting the equipment in-line with the signal flow accommodates testing of the various portions of the chain. The equipment's modular architecture permits the generation of digital pattern, digital I/Q, digital IF, analog IF, and RF signals.

To ensure accurate measurements, this high-tech test equipment must have specifications that suit digital output at rates as high as 400 MB/s and beyond. It also needs to be able to handle high-bit-rate D/A converters, in the neighborhood of 14 bit — 160 MS/s digital-to-analog converters and higher.

New innovations in solid-state waveform memory can accommodate simulations in the gigabyte range. Such deep memory is a key requirement in attaining 60 MHz bandwidth at 160 MS/s sampling rates. Such deep memory also allows sufficient recorded time periods to accurately analyze the waveform.

Finally, direct-to-IF architectures are typically used to achieve wideband RF output for multi-carrier performance. An output plot showing four-carrier UMTS simulation (note the ACP performance on the order of -64dBc) is given in Figure 3.

Test and measurement innovations that provide designers with the ability to both record and playback RF, analog or digital signals are effective tools for shortening design cycles and improving the bottom line. Features such as debugging receiver algorithms, acquiring signals in the field for later analysis, and capturing intermittent phenomena for study make the final design much more accurate and reliable.

Such innovations in mass storage — those that offer several hundred gigabytes of memory enhanced with RAID disk arrays for capturing record and playback — can save the designer work and worry. This unique combination of direct-to-IF architecture, wide bandwidth and deep memory capability provides a critical advantage in testing and debugging next-generation communications products.

John DeMott is vice president of marketing at Celerity Digital Broadband Test. He has years of experience in the test and measurement field and, before going to work for Celerity in 1999, worked with Tektronix for 11 years. DeMott can be reached by e-mail at:
jdemott@celerity.1-3com.com.

The CS2010 Vector Signal Generator is part of the CS2000 instrument series from Celerity Digital Broadband Test, an L-3 Communications company. It was designed to offer advanced test and measurement solutions for multi-standard, multi-carrier applications. Additional configurations in the series include solutions that provide designers with the ability to both record and playback RF, analog or digital signals.