Even an ideal DAC will have harmonics and unwanted spectral energy across the entire band, and these are exacerbated by DAC non-linearities. The standard figure of merit for DAC performance is spurious-free dynamic range (SFDR), measured without a reconstruction filter. SFDR is a measure of the power of the largest spur relative to the carrier from dc to one-half of the DAC sample rate. For a 14-bit DAC, wideband SFDR of -50 dBc to -70 dBc is common. While it is certainly possible to have higher-order DAC spurs at or below the desired output frequency, these spurs often have much lower amplitude (below -70 dBc). The primary means for attenuating DAC spurs is with the reconstruction filter, and a seventh-order low-pass filter will quickly attenuate spurs. Figure 3 shows a typical DAC output spectrum and reconstruction-filter frequency response. The designer should be careful to choose a system clock frequency so that lower-order spurs are not close to the desired output frequency, allowing them to be effectively filtered.

Choosing the correct DAC system clock is an important consideration when using a digital PLL. In the most demanding applications, a high-frequency oscillator can be used to provide the 500 MHz to 1000 MHz DAC system clock directly. However, they can be expensive, and few applications demand them. Many digital PLLs feature an analog PLL clock multiplier that produces phase noise numbers acceptable for many applications. In these cases, the designer can drive the DAC system clock PLL with a common 16 MHz or 25 MHz crystal, or with crystal oscillators in the 16 MHz to 100 MHz range, thus allowing the onboard PLL to generate a 1 GHz system clock. However, the noise of the onboard PLL must be factored in to any jitter calculations.

When choosing a crystal oscillator, the designer should consider the desired output phase noise and stability requirements. For instance, if Stratum-2 clock stability is required while in holdover, then a Stratum-2-compliant oscillator should be used for the system clock. Output phase noise is not only a function of the phase noise of the oscillator, but also the amount of frequency multiplication supplied by the system clock PLL (if used). Using a third-overtone crystal oscillator at 80 MHz to drive the system clock PLL will deliver better overall phase noise than using a 25 MHz oscillator for the same function.

Another fundamental drawback shared by all digital PLLs is that the output frequencies available are generally lower than those possible when using analog PLLs.

Of course, whether an analog or digital PLL is the best option depends on the application. In systems where holdover, reference switching, and loop reconfiguration aren't necessary, the analog PLL presents an attractive option, and one that allows for higher output frequencies. On the other hand, the digital PLL excels in redundant clocking applications where smooth switching, holdover, and well-controlled loop dynamics are needed. Their flexibility and dynamic reconfiguration allow different frequencies on the reference inputs, and a DDS-based digital PLL handles low reference frequencies exceptionally well. Therefore, DDS-based digital PLLs can offer solutions that traditional analog PLLs cannot provide. Because digital logic is used to implement the digital PLL building blocks, a new level of performance and flexibility is achieved, giving designers an alternative to analog PLLs.

However, to overcome the limitations of either PLL design, a powerful combination is a digital PLL followed by an analog PLL as shown in Figure 4. The digital PLL can handle clock switching and difficult frequency ratios, while the analog PLL can further attenuate spurs, multiply to higher frequencies, and perform clock distribution. RFD

Paul Kern is a clock applications engineer in the Clock and Signal Synthesis Group at Analog Devices. Kern earned a BSEE and MSEE from Santa Clara University, Santa Clara, Calif., and has 15 years of industry experience He can be reached at paul.kern@analog.com.

Click here for the enhanced PDF version of this article

Previous 1 2 3