Simulating parameters for hardware modeling before manufacture is no longer an option in today's cost-competitive environments. High speed computers and complex software make modeling reliable, efficient, and accurate.

Modeling and simulating the RF sections of an 802.11 direct-sequence, spread-spectrum (DSSS) system, Bluetooth, HomeRF, or other unlicensed product is an excellent way to minimize design errors, reduce the product development time and contain costs.

Designers encounter many issues, problems and procedures working with 802.11 DSSS RF subsystems.

For reference, the filters, amplifiers, and mixers used in this system simulation have their parameters set to values representative of a commercially available wireless local-area network (WLAN) chip set.

The 802.11 specification allows a data rate of 1.0 Mb/s or 2.0 Mb/s. A 1.0 Mb/s differential binary phase shift keying (DBPSK) modulation is used here. A Barker spreading code of 11.0 Mb/s is used for each of the data bits, which is a ratio of 11:1 (Barker code vs. data). This results in a channel width of 22 MHz.

The transmitter conforms to the IEEE 802.11 spectral mask requirements for transmission. The side lobes are at least 30 dB down from the main lobe. The output power to one of the 11 possible channels is +17.5 dBm.

The simulated system uses most of the ISM band from 2.4 GHz to 2.4835 GHz. Figure 1 shows 11 22-MHz-wide channels that cover the range of 2.401 GHz to 2.473 GHz. The channels are on 5.0 MHz centers.

In a multiple-cell network topology, overlapping and/or adjacent cells using different channels can operate simultaneously without interference if the spacing between the center frequencies is at least 30 MHz. Europe and Japan each have a different frequency allotment in the ISM band.

(Note: An entirely different specification, 802.11b, allows 25 MHz channel spacing and allows two additional data rates of 5.5 and 11.0 Mb/s, using eight-chip complementary code keying (CCK) instead of the Barker code.)

In Figure 2, the transmit in-phase and quadrature (Tx_I” and Tx_Q) digital signal level inputs are applied to the modulator IC. The rate of these I and “Q signals is 11.0 Mb/s. In the modulator IC, the I and Q inputs pass through a 7.7 MHz, five-pole, lowpass Butterworth filter to provide pulse shaping and control of spectral mask. The filtered I and Q signals are then applied to a quadrature modulator. (In reality, the local oscillator (LO) for the quadrature modulator is external to the IC, but this example shows the LO as if it were part of the IC.) The quadrature-modulated 280 MHz IF signal exits the IC to pass through a 17 MHz-wide surface acoustic wave (SAW) bandpass filter before entering the up-converter IC. After the up-conversion to 2.442 GHz, there are several filters and amplifiers in the chain before the RF is sent to the transmitter antenna.

At the receiver, several filters and amplifiers exist before the 2.442 GHz RF is down-converted to a 280 MHz receiver IF. A second 17-MHz-wide SAW filter is used before the IF enters the quadrature demodulator IC. Once inside the IC, the IF is applied to a pair of limiting amplifiers before going to the quadrature demodulator. A two-pole LC filter exists between the limiting amplifiers. The demodulated receive in-phase and quadrature (Rx_I and Rx_Q) signals are then filtered by the same pair of 7.7 MHz lowpass filters that were used in the transmitter section of the IC.

The Rx_I and Rx_Q are normally connected to a third IC, a baseband processor. However, it will not be used in this example. Instead, the receiver's quadrature demodulator will become part of a four-phase Costas loop. The demodulated Rx_I data are then processed by an exclusive-OR gate and differential decoder.

In Figure 3, the output of the data PN token 0 represents the 1.0 Mb\s data input to the system. It is connected to a differential encoder comprised of an exclusive-OR gate and a delay token. The delay time is equal to the width of 1 bit, 1.0 μsec for 1.0 Mb/s. The other input to each exclusive-OR gate is an 11.0 Mb/s Barker code. The exclusive-OR gate will spread the data by modulating it with the Barker code.

Token 113 is a metasystem that generates a Barker PN code sequence having a rate of 11.0 Mb/s. The 11-bit Barker code, 10110111000, has special properties for use in a correlation process. The Barker code generator is an 11-bit shift register that shifts the data pattern as required. As shown, the Tx_I and Tx-Q signals are identical. The input signals are delayed in time so they will line up with the receiver's output.

The transmitter portion of the system is contained in the metasystem token “Qmod2452e6.mta” (see Figure 4).

The first thing the I and Q inputs see is a quadrature modulator, “QMod280e6.mta” (see Figure 5). The modulator accepts digital signal level “I and Q” inputs that are connected to a pair of NOT gates operating as non-inverting buffers. The two buffer tokens are used to simulate the input comparators on the IC. The buffers output square waves before any filtering takes place. This output drives the filters at a constant 550 mV peak-to-peak. The 7.7 MHz, five-pole Butterworth filters are used to reduce the side lobes to about 36 dB below the main lobe at the output of the modulator. These filters are used to meet the IEEE 802.11 spectral mask requirements of a -30 dB side lobe maximum at the transmitter output. Downstream, the non-linearity of the various mixers and amplifiers will cause this -36 dB value to grow toward the -30 dB value.

The SAW filter is modeled by using a 954 tap, bandpass finite impulse response (FIR) filter. The frequency response of this filter is shown in Figure 6.

The output of the quadrature modulator goes to a SAW filter with a center frequency of 280 MHz, and a bandwidth of 17 MHz. The particular device chosen for this application has the following specifications, interpreted from their graphs:

Center frequency: 280.0 MHz
Loss at: -8.5 MHz = -3.0 dB
Loss at: +8.5 MHz = -3.0 dB
Loss at: -19.4 MHz = -50.0 dB
Loss at: +19.4 MHz = -50.0 dB
Passband ripple: = 1.0 dB
Insertion loss: = 10.0 dB max
Passband delay: = 0.234 μsec

The filter specification lists a maximum loss of 10.0 dB. An attenuator is used after the filter to insert a typical loss of 7 dB and the resulting noise figure into the system. This attenuator-after-filter plan is used for most of the filters in the system. The second attenuator after the FIR filter is used to adjust the power output of the channel to +17.5 dBm.

After the FIR (SAW) filter, the 17-MHz-wide IF is up-converted to a 2.442 GHz RF carrier. A metasystem, TxUpConvert3624.mta (see Figure 7) uses the parameters from the data sheet for the desired mixer. Its gain plot may be seen in Figure 8. For the simulation, an analog two-pole, 0.5 dB linear phase filter is used.

Between the up-converter and the transmitter power pre-amp, there is a two-pole, LC bandpass filter with the following specifications:

Center frequency: 2.442 GHz
Loss at: -42.0 MHz = -3.0 dB
Loss at: +42.0 MHz = -3.0 dB
Loss at: -440.0 MHz = -20.0 dB
Loss at: +440.0 MHz = —
Passband ripple: 1.5 dB
Insertion loss: 2.7 dB max

The pre-amp is part of the same IC that has the IF-to-RF up-converter. It is followed by a two-pole filter. Between the transmitter power pre-amp and the power amplifier, there is a two-pole, dielectric resonator-coupled bandpass filter. An analog two-pole, 0.5 dB linear phase filter is used to simulate this filter. The bandpass filter, for RF LAN use, has the following specifications:

Center frequency: 2.450.0 GHz
Loss at: -50.0 MHz = -3.0 dB
Loss at: +50.0 MHz = -3.0 dB
Loss at: -280.0 MHz = -20.0 dB
Loss at: +280.0 MHz = —
Passband ripple —
Insertion loss: 2.0 dB max

A gain plot of this pre-amp output filter is similar to the filter in Figure 8. This same filter is used twice more in the path to the transmitting antenna.

The power amplifier is a stand-alone IC. It is followed by two, two-pole filters, in series. The frequency spectrum at the transmitter's output is shown in Figure 9. The two nulls are ±11.0 MHz away from the 2.452 GHz center frequency. The side lobes are down about 30 dB relative to the peak. This completes the transmitter chain.

In Figure 3, an attenuator token, set to a loss of 90 dB, is used to simulate the path loss between the transmitter and receiver.

The receiver's input noise is modeled using an adder token with a thermal noise source token set as follows.

Resistance: 50Ω

Temp: 300° K

This noise represents a receiver with a front-end noise temperature of 300°K (27°C or 80.6°F) due to the antenna. This is also a convenient place to inject interference test signals.

The input to the receiver (Figure 10, RxQdemod2442e6down.mta) uses the same two filters used at the transmitter's output. Also, there is a loss due to a Tx/Rx switch. Two low-noise amplifiers are in series; the second is an RF/IF converter IC.

As in the transmitter, there is another two-pole LC bandpass filter between the output of the second LNA and the input to the RF/IF converter IC. The LO for the active mixer uses a pulse train token. At the mixer's output there is a SAW (FIR) filter with a 280 MHz center frequency. It has the same specifications as the FIR filter in the transmitter.

The output of the FIR (SAW) filter goes to a pair of limiting amplifiers and then a quadrature demodulator (Figure 11, RxQdemod280e6_5.mta).

Each of the limiter amplifiers is modeled by setting an RF amplifier token to the following parameters:

Gain: 45.0 dB
3rd order Int: 4.9 dBm
N.F.: 9.0 dB
1 dB compression point: -4.9 dBm

The 1 dB compression point of -4.9 dBm gives a clipped output of ±200 mV. (The application note 9746 shows a LC circuit with a differential input/output that is used between the two limiting amplifiers.) A RF LC-quadrature tank token is used for this LC filter between the two amplifiers. The values in Figure 12 accomplish the task of a 48 MHz bandwidth (-3 dB) with some gain at the center frequency (Figure 13).

In Figure 11, the FM token is the voltage-controlled oscillator (VCO). The VCO's gain parameter is set to 15 MHz/V. The parameters of the two mixers are set to match the device's' data sheet. The 7.7 MHz, five-pole filters are the same as the pair used in the transmitter.

An exclusive-OR gate is used to despread or remove the Barker code modulation from the information-bearing signal. The Rx_I output of the quadrature demodulator is one input to an exclusive-OR gate. The other input to the gate is from the receiver's Barker code generator. A differential decoder follows the despreading circuit.

The differential decoder exclusive-ORs the data with delayed data. The delay is set equal to the reciprocal of the data rate, 1.0 e^-6 seconds.

A filter follows the decoder circuit. Its parameters are two-pole, Bessel, lowpass, 0.5 MHz (1/2 of the data rate).

The entire system will function without the differential encoder and decoder, however, the received data may or may not be inverted. This puts an unnecessary burden on the baseband processing. When the differential encoder and decoder are used, the data information will always have the correct polarity.

The four-phase Costas loop operation is similar to a PLL. In Figure 3, the Rx_I and Rx_Q outputs of the quadrature demodulator connect to the four-phase Costas loop phase detector in Figure 14. (Actually, the four-phase Costas loop is the combination of the quadrature demodulator and the processing in Figure 14.) Figure 15 is the Bode plot of the PLL filter after the summing token. The RC parameters are set to produce a lowpass filter with a -3 dB point of 0.1 MHz, and an ultimate loss of -12 dB. The output of the phase detector is an error signal that drives the VCO.

Simulation of the full system takes only 16.3 seconds on an 866 MHz Pentium III computer. The simulation results are shown as three plots in Figure 16. The top and middle plots have the same elapsed time of 10 μsec.

The top plot is an overlay of the rectangular 1.0 Mb/s data_in signal and the smooth, filtered, data_out signal. The middle plot is an overlay of the 11.0 Mb/s Tx_I and Rx_I signals. Close inspection of the middle plot will reveal the 10110111000 pattern of the Barker code.

The bottom plot is the power spectrum of the received signal, Rx_in, with a path loss of 90 dB. The visible part of the transmitted spectrum is 22 MHz wide, while the -30 dB side lobes are below the noise floor. The remaining task in the processing is to make a hard decision on the received data bits and perform a bit-error-rate (BER) analysis. The BER is the standard figure of merit for digital communications systems. The system parameters can be “tweaked” to produce minimum BER (maximum range).

The simulation of the RF portion of an 802.11 WLAN system has been detailed. The parameters were based on existing chip sets and commercially available parts. The simulation engine allows for accurate representation of the system components.

Stephen H. Kratzet is director of electronic design at Elanix. Kratzet joined Elanix in 1992. He is responsible for managing Elanix's RF analog, digital and DSP hardware designs. Prior to his work at Elanix, Kratzet worked for electronics consulting group Mullet Associates for 12 years. Prior to that, he spent 12 years at Solatron, designing automatic assembly and test machines. Kratzet can be reached at Elanix, 5655 Lindero Canyon Rd., Ste. 721, Westlake Village, CA 91362. Tel. 818.597.1414. e-mail: Stevek@elanix.com

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