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Circuit linearity has always been a major design issue. Design performance is limited by intermod performance at the top end of the dynamic range and by noise on the bottom end. Intermod and noise performance are at odds with one another and many times improving the performance of one means degradation of the other. Current simulation techniques work well at a circuit level but poorly whenever several nonlinear stages are cascaded together. Despite advances in simulation technology, engineers are still using spreadsheets and cascade analysis tools to determine critical performance parameters. These simulation techniques are error prone and only provide a rough estimate of idealized performance.

Cascaded equations were derived to help designers determine the performance impact when nonlinear stages are cascaded. Real world problems can be difficult to solve. Many times, assumptions are simplified so that basic operations can be understood and analyzed. Some simplified assumptions made during the derivation of cascaded intermod equations are:

• all frequencies are treated equally,

• only in-band interference is assumed,

• all stages have been perfectly matched,

• only two equal amplitude tones are used,

• intermods never travel backward (reverse isolation is assumed to be infinite), and

• intermods arriving from other paths are assumed to be zero.

A classic example of where these assumptions fall short occurs when the input intercept point of a receiver is calculated. The input intercept is determined by analyzing the amount of in-band intermods generated by out-of-band interferers. Out-of-band interferers are generally attenuated by intermediate frequency (IF) filters. Traditionally, cascaded intermod analysis is only carried up to the first IF filter since cascaded intermod equations cannot encompass out-of-band attenuation from interfering signals. Assumptions are made that these interferers are eliminated from the IF filter and beyond. These assumptions, necessitate creating a schematic for the intercept point, another one for noise figure, etc., which become a nightmare when modifying or updating the design since changes have to be made in so many different places.

Another major issue with cascaded intermod equations is that they lend themselves to a spreadsheet-type of analysis. Spreadsheets suffer from the following deficiencies:

• every engineer has a custom spreadsheet, which makes it difficult for engineers to share designs and standardize on tools,

• version control is difficult,

• spreadsheet analysis is error prone; a single mistake can propagate throughout the whole design,

• spreadsheets are only as good as the engineer who wrote it,

• circuit simulation results cannot be used to validate the architecture before committing to layout, and

• no optimization.

A new simulation technique allows users the ability to simulate intermod and noise performance comparable to what would be seen in the real system. The user captures the block diagram and applies signal sources to the system. The simulation engine propagates all signals, noise, intermods, harmonics and everything else created along the way to every node in the system. With the click of the mouse, full-frequency amplitude and phase spectrums can be viewed at any node. This eliminates the burden of adding measurement icons to schematics and re-running simulations every time a new measurement is needed. Simulation time of broadband spectrums is much faster than traditional nonlinear simulation techniques.

The time needed to learn this new technique is little more than that required to learn how to capture block diagrams. Why spend time fussing formulas, validating equations, and formatting information when the block diagram needs to be captured anyway for documentation purposes? Why wait until hardware shows up in the lab to validate the cascaded analysis when circuit simulation results can be substituted back into the architecture before layout begins? Why settle for less accurate results due to restrictive assumptions when all sneak paths are automatically analyzed? Why not create a block diagram, one that can be reused in the same tool throughout the whole design process instead of making copies for each test and measurement? Why wait for the technician to debug the design to identify problem intermods when complete spectrum amplitude, phase, origination, and traveled path information is available for every data point in the spectrum?

The first example shows a ‘percent third-order intermod’ and a ‘total third-order intermod’ measurement on a level diagram for a simple cascaded lineup. From the level diagram in Figure 1, the designer spots the weak link in the intermod chain to be the first amplifier. More than 40 RF measurements are available to plot on a level diagram or show in a table. There is no need to write equations or work with spreadsheets.

These intermods were created from three carriers at 4100 MHz, 4200 MHz and 4400 MHz. Intermods were measured in the 4000 MHz channel. Both amplifiers will create intermods from all combinations of carriers. Third-order intermods will be created in the 4000 MHz channel by the 4100 and 4200 pair and the 4200 and 4400 pair. Figure 2 shows the spectrum at the output of the cascade. This simulation technique enables the user to graphically see and measure all intermods, their combinations, power levels, phases, and frequencies with their proper relationships to each other. From the plot we learn this new technique provides: 1) broadband noise analysis, 2) signal bandwidth with spectral density, 3) the ability to see signals below other signals including noise, 4) simulation of the dynamic range and numerical resolution of noise is a non-issue (the dynamic range has intentionally been decreased to give better visibility in a published article), and 5) identification of every intermod component that contributes to its total (each new spectrum color at the same frequency represents another piece of the spectrum). This entire simulation with three independent carriers and broadband noise (DC to 21 GHz) ran in a fraction of a second on a 500 MHz Pentium III.

A nonlinear circuit simulation technique called harmonic balance performs vector addition on all common frequency components thus destroying all hope of spectrum identification and the ability to see in-channel signal-to-noise ratio. Furthermore, harmonic balance has no concept of bandwidth, broadband noise or directional power flow. Also, simulation time for this same example would take orders of magnitude longer. Harmonic balance is a great nonlinear circuit simulation technique but its application to RF architecture and system design is limited.

Example 2 illustrates how intermod simulation with the new technique is not limited to simple linear cascaded lineups. Indeed, the topologies can be arbitrary. Figure 3 shows a doubly balanced second- and third-order cancellation amplifier. Four parallel amplifiers exist in two pairs. The top and bottom pairs of amplifiers use 90° splitters/combiners so third-order products are cancelled at the output of each pair. The top and bottom pairs of amplifiers use 180° splitters/combiners so second-order products are cancelled at the output of the overall amplifier.

Simulating this architecture in a spreadsheet or cascade analysis tool is difficult and several simplifying assumptions must be made. However, topologies like this are no problem with the new technique. Four paths have been created in this example. One path through each amplifier. All four paths have been plotted on the same level diagram as shown in Figure 4 (the node sequence at the bottom of the diagram represents one of the paths). From this level diagram we learn several things about this new simulation technique. We see that intermods are present at the amplifier input (port 1). All amplifiers have reverse isolation that causes the non-linear spectrum created by individual amplifier to be propagated backward. Since reverse intermods don't go through the same phase changes as forward traveling intermods, their power doesn't cancel at the amplifier input as it does at the amplifier output.

The simulation technique enables users to explore behavioral model parameters like never before. It can address questions such as, what happens when the gain or phase of the components become unbalanced? What gain and phase balance is needed to maintain a target level of performance? What splitter isolation and reverse isolation is required to achieve the target performance? What type of performance would be expected over variation or Monte Carlo analysis? For example, the gains of the amplifiers in the previous example were changed from 20 dB to 18 dB, 19 dB, 20 dB, and 21 dB respectively. Figure 5 is a level diagram illustrating the affects of gain imbalance on overall amplifier performance.

The overall intermod performance went from -100 dBm, for perfectly balanced amplifiers, to -30 dBm for a poorly balanced system. Until now, insight into these types of design issues was virtually impossible. Debugging, troubleshooting, and redesign were based on lab measurements. But from lab instruments, it is difficult to know what contributions are due to amplifier reverse isolation, splitter isolation, gain balance, and phase balance.

Traditional limitations associated with cascaded analysis have been removed. A new simulation technique (using SPECTRASYS in the GENESYS design suite from Eagleware) is more reliable and insightful for examining RF architectures and systems. Weak links are identified and root causes are available to the designer. Complicated, individualized, custom spreadsheets, math packages, and ad hoc tools are no longer needed. Non-linear and broadband noise simulation time is fast and not restricted as opposed to conventional harmonic balance, time domain, and envelope simulation techniques.

Rulon VanDyke is the lead engineer in systems simulation at Eagleware Corporation, Norcross, Ga. He received a Bachelor of Science degree and Master of Science degree in electrical engineering from Brigham Young University in 1990. For 10 years, he designed first-, second-, and third-generation digital cellular transceivers and base stations for AT&T Bell Labs and Lucent Technologies. He can be reached via E--mail at: rulon@eagleware.com.