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Data conversion devices are now common and will become even more so as new applications arise. For example, the dream of the digital software radio, especially for base stations of cellular and PCS, is closer now then ever. A high-quality front end is digitized, then processed for any air interface desired, including the global system for mobile communication (GSM), code-division multiple access (CDMA), and universal mobile telecommunications system (UMTS).

For such processing, ultra-high dynamic range, multibits and high-speed A/D (and D/A) converters are necessary. In such high-quality devices, one must be extra careful when choosing the clocking source. Excess phase noise (or jitter) can easily degrade the performance of the data conversion devices.

PLL synthesis technology is generally recognized as the optimum solution for generations of high-frequency timing sources with ultra low-jitter requirements. This article will review the effect of jitter on the performance of data conversion devices and the effect of phase-noise profile on clock jitter.

Data conversion devices (analog-to-digital (A/D), and digital-to-analog (D/A) digitize analog signals or convert digitally represented signals to the analog domain. While D/A technology has been running >1 GHz for a few years now, A/D conversion at ultra-high speeds (as high as 300 MHz) with high resolution (as high as 14 to 16 bits) is only now coming of age. Digitizing involved quantization causes an inherent error.

Using N bits, quantization error for data conversion devices is very easy to calculate as follows:

Signal energy, assuming a sine, has a peak-to-peak of 2^N. Therefore, it has an RMS value of 2^N-1/√2, and power level of S=2^2N/8.

The quantization error can occur equally randomly in the uncertain area, ±0.5. Its probability density function is flat (p(x) = 1) and its power can be easily calculated to be:

Therefore, the signal-to-quantization noise ratio (S/N_q) is given by 1.5 × 2^2N or 6N+1.78 dB.

This is a well known and fundamental ratio in DSPs and every extra bit adds theoretical 6 dB performance.

This noise has a power spectrum of (Sinx/x)² where x=πƒ/F_c. F_c is the sampling (clock) frequency.

To simplify the calculations, assume that the noise spectrum (see Figure 1) is flat with a single sideband (SSB) bandwidth (BW) of F_c/2 Hz (fraction of dB error).

It is now easy to calculate the approximated noise distribution generated by such a device, due to quantization, based on its sampling frequency.

For example, a 14-bit A/D running at 100 MHz generates a (SSB) noise floor of about -85.8-10 log(100^e6)+3 ≈ -162.8 dBc/Hz. Hence, the theoretical noise floor generated by quantization is very low.

To this point, all has been assumed to be ideal. The focus will now shift to the sampling mechanism.

An analog signal is being sampled by a clock that has some jitter. A simple relationship between this jitter and the effect it might have on quantization error is desired.

All real signals have a phase-noise spectral profile, as shown below (see Figure 2). This noise creates jitter, which will therefore sample the signal at the “wrong” places and create an amplitude error, similar to reducing the converter's accuracy. The jitter allowed without affecting converter accuracy will be determined.

Generally, if the signal's spectrum can be described by L(fm) (its spectral distribution), then the phase (or time) jitter can be derived from that spectrum by:

where F_o is the center frequency, ф_j is the phase jitter in radians, ƒ₁ and ƒ₂ are the frequency range of integration, T_j is time jitter.

The signal has a certain bandwidth and will be represented by a Sin-like (green) wave, sampled as shown by the rising edge of the clock signal (red). i is the running time (sample) index. (See Figure 3.)

Suppose the signal is 2^N-1Sin(2πF_st) sampled at F_c rate, then note the following:

• The signal will be most sensitive to any sampling error around zero crossing. That is where the sine is changing the fastest (there will be almost no sensitivity if we sample at the peak as Sine is almost flat there).

• For the same reason, signal bandwidth (speed) will have a direct effect on the error. Slower signals are less sensitive to jitter. Therefore, jitter will have an effect that is related linearly to F_s/F_c.

By sampling the sine at 0 it is easy to calculate the jitter that causes the converter to read 1 (or -1) instead. This affects the converter's resolution. Such error will have an effect similar to using a converter with less bits.

Given that the signal slope is ≈ 2^N-1 • 2πF_s, and jitter causes an error from 0 to ±1, the time jitter allowed is T_j = 1/2^N-1 • 2πF_s.

Because time jitter is related to sampling F_c by T_j = ф_j/2πF_c, it can be concluded that the phase jitter allowed in the clock is given by:

In the worst case, signal bandwidth is ½ of the sampling clock (Nyquist condition). This calculates to ф_j = 2^-(N+2) RMS.

An “arbitrary” assumption is made that the required jitter is to be at least four times better (when sampling, peak-to-peak jitter this number is arbitrary, 4:1 (like 4σ), to be practical and keep the equations simple).

Hence, in this article the assumed required phase jitter is ф_j = 2^-N rms.

These are tough numbers. A 14-bit converter requires a clock that has 61 μrad or 0.0035° noise (jitter in degrees is the same in radians multiplied by 180/π), assuming that the signal BW is close to ½ F_c. For reference, most cellular synthesizers require 2° rms, or less, noise.

PLL is the technology of choice for generating accurate signals, as well as for having low power, accuracy, flexibility and economy. PLL circuits are mature and achieve excellent performance with lower voltage and overall power.

PLLs include five basic functions: a crystal (xtal) reference, a voltage-controlled oscillator (VCO), a phase detector, dividers, and a loop filter.

For generating low jitter signals above 50 MHz, a PLL in combination with a clean xtal reference is used. PLLs offer simplicity, economy and low noise floor in comparison with direct multipliers, which are bulkier and significantly more expensive.

Most PLL circuits designed for timing use a third-order loop design (second-order filter).

F_r> is the xtal frequency and F_o is the output. At this stage, the assumption is made that the reader is familiar with basic PLL concepts.

A PLL has its own noise mechanisms. The majority of random noise in timing devices comes from the PLL's phase detector/charge pump (PD/CP) circuits, and the VCO.

The CP noise is multiplied by the PLL transfer function, which acts like a band-pass filter (in the baseband analysis, it looks like a low-pass filter); VCO noise is multiplied by the loop error transfer function, which has a “high-pass” characteristic.

Therefore, integrated phase noise depends on the range of integration as determined by:

Note that half of the noise comes from the wideband floor noise.

Everything calculated in regards to ADCs obviously applies the same way to DACs. Another way of looking at the results is to state that the jitter that can be tolerated is generally given by:

T_j ≈ (2π • 2^N • F_s) - 1

Figure 7 shows the jitter one must require from the clock to meet certain signal bandwidth and N number of bits (signal is a 1 to 100 MHz, 8 to 16 bit converter) without violating quantization error (probability is Gaussian with 4σ).

Jitter and phase noise are similar representations of the same phenomenon: the random imperfection of timing devices from the ideal zero-crossing time location. The signal demonstrated above is of very high quality. Still its jitter might not be sufficient for some demanding applications.

Note that the jitter was correlated with signal bandwidth. If, instead of a 240 MHz signal spectrum (for a 480 MHz sampling) the bandwidth was down to 25 MHz (cellular base station bandwidth), jitter could be relaxed by ˜ 10:1.

These requirements add pressure on the quality of the xtal used. PLL circuits must exhibit excellent phase noise and VCOs must possess demanding qualities.

A solution to the VCO requirements is to use surface acoustic wave (SAW) devices. While excellent filter devices, they are narrowband and apply to single-frequency applications only.

Furthermore, such VCOs require narrow loop (<500 Hz) with excellent CP phase noise (see Figure 8). On the other hand, a quality LC VCO (see Figure 9) at 600 MHz requires a loop in the 10 to 20 kHz range, again with excellent CP noise characteristics.

Jitter measures behavior in time and represents an integrated number, while the other (spectral phase noise) measures accurate noise profile in the frequency domain and allows the design, analysis and measurement of the exact noise profile.

Modern digital scopes cannot practically measure below 1 psec jitter. Phase noise measurement, on the other hand, can be measured using almost any synthesized spectrum analyzer.

Therefore, many engineers prefer to use a spectrum analyzer not only for absolute measurements, but also for comparative analysis. At least this offers an option for comparing among competitors who demonstrate 1 psec jitter (the limit of most digital scopes).

Figure 10 shows a typical graph of the concepts for a 2500 MHz clock and a commonly available PLL. Its specifications are shown in Figure 10.

To design accurate and functional high-quality data conversion devices, ADC and DAC, requires very low jitter clock signals. As ADC's performance improves and speeds increase, integrated phase noise of 2^-N (for an N bit converter) requires not only excellent phase noise but also a high-quality noise floor.

When designing these high-quality clocks, a quality VCO and a low-noise PLL chip must be used to achieve the tight requirements for high-speed circuits.

In addition, many of the converters require differential emitter-coupled logic (ECL) clocks, which are derived from ECL application-specific integrated circuits (ASICs) converting sine to positive emitter-coupled logic (PECL) devices. These gates sometimes add phase noise and especially noise floor. Their use must be weighted carefully, based on experience gained, as they are available from multiple sources with varied performance characteristics.

Additionally, clock timing for data conversion can directly affect the converter accuracy and effective number of bits. Hence, its dynamic range and noise floor — parameters of great importance in the applications where wideband signals or multiple signaling (base stations for example) are critical.

The choice of the right PLL circuit is also critical, as shown by the simulations in this article. Finally, low phase noise for the phase detector and CP circuits are critical as well, and both active and passive loops can be used.

1. Data sheet of PE3335, Peregrine Semiconductor PLL chip.

2. W.P Robbins, “Phase noise in Signal Sources,” Peter Peregrinus, London, 1982.

3. Bar Giora Goldberg, “Digital Frequency Synthesis Demystified,” LLH publishing, 1999.

4. Peregrine Semiconductor, AN 13, “Phase noise Demystified.”

5. James M. Bryant, “The Effect of Clock Noise on Sampled Data Systems, ADI, 2001.

Bar-Giora Goldberg is President and CTO of Vitcom Corporation, and formerly technical director of Peregrine Semiconductor. He received his B.S. and M.S. from the Technion Haifa. Goldberg co-founded Sciteq, which pioneered DDS and Fractional-n technology. His expertise is in the areas of Satcom, fast hopping systems, adaptive antenna, communications, spread spectrum, frequency synthesis and system analysis. Goldberg teaches signal generation with Besser Associates and CEI Europe. He can be reached by e-mail at: giora18@tns.net