Click here for the enhanced PDF version of this article
For a pdf version of this article, including diagrams.

The number of challenges facing RF designers continues to build as customers and service providers push for devices that communicate seamlessly among myriad services and protocols. Additionally, the demand for more services and bandwidth to accommodate the multitude of new features is rapidly advancing down the development pipeline, creating more challenges for those trying to place extra functionality into the small form factor of hand-held wireless systems.

The growing rift between analog and digital circuitry and the compromises that result from mixed-signal process technology used to produce ICs for this market are making it more difficult for device designers to meet demands for more services and capabilities.

But new technology is making three-dimensional (3D) semiconductors a viable alternative to mixed-signal, system-on-chip (SoC) technology that is widely in use. Three-dimensional semiconductors are now offering solutions for some of the most vexing challenges facing designers in terms of the integration of devices and the need to integrate a growing feature set in ever smaller packages. Furthermore, 3-D ICs can circumvent some of the roadblocks in process technology that have prevented the practical integration of best-in-class analog devices with the best-in-class digital devices. Moreover, all of this is coming with better time-to-market, improved power consumption and reduced cost compared with the two-dimensional SoC methodologies that are now the mainstream.

Just as RF designers build a single device that communicates with all the standards that are now floating out in the market, new standards emerge and reset all expectations. First, there was old-fashioned analog. Now, there are standards such as CDMA, 802.11 and Bluetooth.

By examining cell phone design itself, it becomes easy to determine that a few challenges exist. One challenge is that a higher-bandwidth datastream is needed for the devices as well as a way to engineer more sophisticated processing capability.

The power that the phone needs to communicate is directly related to the environment in which it is used. Most cell phone voice conversations don't require a great deal of power. But if a high-bandwidth connection were used for any data or video service, today's batteries would quickly run down.

The possibilities for wireless connectivity are remarkable, but the opportunity to sell large volumes of any one particular model of phone is negligible. The more likely scenario is that there will be a swarm of products in which each unit sells in much smaller volume. Proof of this also exists in the Japanese phone market where no major players like Nokia or Motorola dominate. Instead, at least 10 companies are scrambling for their share of that market. That's the kind of company structure and product rollover that you get with quick-turn markets.

On the other end of the spectrum, a manufacturer commits to a set of features and builds a phone; the design sells reasonably well in its first six months, and the manufacturer is able to gain some market share. After that, the design is virtually obsolete and a new design is needed before the company's market share gains start slipping.

The rewards are going to be taken by the people who innovate quickly and who have a mix-and-match strategy across the board. It rewards those who can support markets that require product changes on a six-month interval and who can support up-front investments and are consistent with a lesser total volume in any one product.

What 3-D ICs can offer is a feature integration strategy that supports these quick turns in consumer markets.

To see how 3-D integration could help an RF designer, let's look at a typical design challenge and how it would be solved with contemporary methods. Then we will look at how it could be solved with a particular 3-D integration strategy and compare the different methods.

With many of the functions of the phone being integrated, the phone is being asked to do more jobs. It has to be serviceable on more frequency bands, and every one of these bands adds an army of passive components.

In 2001, a Nokia mainline phone had a part count of about 460. In 2003, that same phone had a part count of about 320. That's a significant reduction in parts. Most phones today have a phone board and an applications board. The phone board only has three or four or perhaps five chips on it and several resistors, inductors and capacitors.

Assembly services have done an amazing job figuring out how to package these components in an efficient manner. Special tooling has been developed to reduce cost. But the bottom line is that whenever parts are handled, there is an associated cost. One of the primary goals of phone manufacturers is to integrate those components. They would like to sweep them up and build them like a chip to reduce the associated handling costs.

Some problems exist with this sweeping up and building like a chip idea, though. One problem is that if you take a silicon wafer and decide to build an inductor, the performance is not nearly as robust as the discrete device. In reality, many of these devices won't perform as well as the discretes you are trying to replace. The silicon substrate, which is great for building silicon transistors, is horrible for building passive devices because it is conductive. So when you have an inductor or a capacitor, it has fields associated with its operation. They cause currents in the substrate in response to the field variations. Those currents are a parasitic loss component, which compromises the performance.

With 3-D integration technology you can decouple the constraints that are driving substrate selection in the direction of silicon and use a substrate that's well adapted to making passive components. An RF designer can incorporate those and will create a landing zone for the active electronics, then drop those chips on to it. The designer will replace all of these discrete components and their associated assembly technology with the advantages of thin film processing at wafer scale to build integrated networks.

CMOS scaling trends that are favorable to digital designs are resulting in increased leakage, loss of dynamic range and reduced gain. These factors will render the analog portion of many mixed-signal designs impractical beyond 130 nm.

It doesn't seem like the world is going to coalesce on wireless standards. It's pretty clear that China is going to enforce its own standard. The Japanese standards are different from the European and American standards. Phone manufactures are facing the inevitability of needing to build different models for different markets.

Because some of the most lucrative users travel extensively, the idea of a world phone may remain illusive. Phones will have to support multiple bands. The way that is done today, the phone contains a separate radio section for each band, and they share virtually no circuitry.

If we can reduce the part count in the front end of the phone by integrating passives and actives, we have a chance to achieve a phone where the front-end can be programmed to the analog functionality similar to the way an FPGA can be programmed to different digital functions.

As long as we have a forest of resistors and separate power amplifiers, it's hopeless. But if we can start to integrate these components on a wafer with active electronics that can act as switches, we have at least started on a path that can produce a software-configured radio.

With a wafer-bonding approach, all of the devices must be in wafer form because all processing (except for the actual die placement) is performed at wafer level. The wafers can be sourced from any vendor, and any combination of wafer diameters can be processed. Using a recent development product as an example, the flexibility of the approach can be illustrated.

Until recently, most of the integration within a cellular phone has been in the baseband area as evidenced by stacked Flash (NAND & NOR) and RAM memory in a single package, as well as the incorporation of the microprocessor and DSP functionality together on the same die. These combinations, although not easy, were made more straightforward by rapid advances in CMOS semiconductor geometry scaling, packaging developments, readily available IP cores, and the inherently lower frequency of operation. For RF functionality, the drive for size reduction and integration has been more difficult. It has taken the development of new substrate materials, better RF circuit modeling, and advanced manufacturing and packaging techniques to begin to integrate RF circuitry on a scale even close to that seen in the baseband area.

A purely hypothetical example of what might be done with RF integration can be developed using a product that has recently been introduced to the market. Figure 1 shows a picture of a dual-band antenna switch developed for use in GSM applications. The advertising says this is currently the “world's smallest antenna switch module” and represents the best effort to date in the integration of this type of RF functionality into a single, small package.

Three separate dies are mounted onto a printed circuit board: a GaAs PHEMT SP4T switch, integrated passives (eight capacitors and four inductors) in GaAs, and ESD protection also fabricated in GaAs. It is difficult to see exactly, but there appears to be about 18 gold wire bonds to connect and route all of the signals.

The difficulty of 3-D integration with RF components is that many times the design depends on an air interface above the circuitry. This is especially true with the four large inductors visible on the integrated passives die, so it would not be advisable to mount another die on top of this or try to mount this upside down without an air cavity underneath.

Instead of an organic printed circuit board (FR4), the base substrate onto which the various dies are mounted is one in which the passive components can be integrated while still maintaining high-Q and low loss. The substrate materials in use today include GaAs, high resistivity silicon (HRS), silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). The wafers containing the functional circuitry are first thinned to the desired thickness to make the interconnect distances shorter and to reduce the overall z-dimension so standard packaging can be used. Care must be taken in the thinning process so that the RF performance of the circuitry is not adversely affected as the E-M fields penetrate some distance into the substrate.

Next, the individual die can be mounted either circuit side up, which provides an air interface and easy access to bond pads, or circuit side down, which reduces the interconnect distances to just a few microns. A circuit side down approach would probably require a cavity beneath the circuit areas to prevent performance degradation.

Circuit side up: This approach would look similar to the photograph in Figure 1 in that the individual die would be mounted on the wafer substrate with the circuit side up. However, the wirebonds would be replaced with over-the-edge connections as shown in Figure 2.

This is not the best way to make RF connections, but the total path length is the thickness of the die itself (less than 100 µm after thinning) before landing on the underlying substrate. The substrate wafer would contain all of the passive devices, which can be located close to the active circuitry and are interconnected with vias.

Circuit side down: This approach places the circuitry face down on the substrate, which provides a short path length (< 20 µm) to the interconnect networks within the substrate but may require a small air cavity beneath the RF circuitry to reduce the effects of contacting the substrate directly (Figure 3).

A peripheral ring of approximately 200 µm is required around the RF die to ensure a good seal. All of the interconnections with this approach are made with through-die vias, which provide a short, low-loss path.

One of the most active areas of interest in RF development is the integration and interconnection of RF circuitry. Many of the production processes developed for digital devices have been applied to analog and RF with great success. However, as operating frequencies continue to increase, alternative methods have been developed to improve system performance and reduce cost.

Elimination of wire bonds: Although wire bonding is the most commonly used method of packaging, at higher frequencies of operation, the impedance of the wire becomes a significant factor and must be accurately accounted for to maintain a good impedance match. In general, a wire bond is several millimeters in length and will add 1-2 nH of series inductance and 50-100 fF of shunt capacitance. At higher frequencies, such as those used for the cellular PCS band, Bluetooth or Wi-Fi, this series inductance translates into greater insertion losses and reduced bandwidth. By comparison, a through-die via interconnect in 3-D integration is a few microns in length and will add only about 0.1 nH and 10 fF. Additional losses are caused by the variability of the length of the wire bonds themselves, which can vary ±150 µm and results in uncompensated variations in impedance. The through-die via interconnect is repeatable and consistent due to the precise methods available with wafer scale semiconductor processing.

One of the reasons development effort has been spent in flip-chip packaging for RF circuits is to remove the parasitic losses caused by wire bonds. The resulting performance is much improved because of the short die-to-substrate distance. The unit-to-unit variation is also reduced because the ball height and shape are consistent and predictable. The major difficulty with flip-chip packaging is getting rid of heat because the only thermal path is through the small solder balls and epoxy underfill to the substrate. The epoxy underfill is necessary for mechanical reasons because of the stresses from CTE mismatch between the die and underlying substrate. However, the underfill has poor thermal conductivity. Therefore, most flip-chip RF devices are restricted to low-power applications.

Thermal issues: Many industry experts agree that the limiting factor to continued miniaturization and integration is not for technical issues but rather thermal issues. It is simply becoming more difficult to remove the heat quickly enough to maintain acceptable junction temperatures. As mentioned previously, flip-chip packages, although good for RF performance, are limited to low-power applications because the thermal path to ambient is so poor. Wire bond packaging is much better thermally because the entire backside area of the die is in the thermal path. Unfortunately, substrate materials good for RF performance (GaAs, InP, etc.) have only fair thermal conductivity as seen in Table 1. The advantage with 3-D integration is that the RF substrate can be thinned to minimize the thermal resistance in that material, but it can be bonded to a highly thermal conductive material (Si, BeO, SiC). This means the 3-D integrated package can handle the higher thermal densities seen both in higher-power devices and small, highly integrated devices.

EMI and shielding: Integrating RF devices is a challenge because of the tendency for the EM fields to couple or radiate to the surrounding circuitry, which increases loss and reduces isolation. Wire bonds are particularly prone to these problems. The 3-D approach has much better EMI characteristics because interconnect distances are short and isolation vias can be placed around sensitive signal paths to further improve isolation. In addition, copper metallization can be deposited on the underlying substrate to provide a Faraday shield beneath the active devices as well as a good ground plane for stray field termination.

RF designers facing the challenges of integration have many concerns with regard to protocols, standards, time-to-market, design costs and process technology constraints. Three-dimensional integration provides a methodology to address many of the concerns and help designers build market share-winning products in low-volume markets that demand quick-turn product strategy and high levels of functionality.

Robert Markunas is vice president of Market Development at Ziptronix. He is responsible for creating, developing and maintaining customer relationships at Ziptronix. Markunas spent the majority of his career with North Carolina's Research Triangle Institute International (RTI), in the role of director of the center for semiconductor research. He holds a Bachelor of Science degree in Engineering from Massachusetts Institute of Technology and participated in graduate studies in Electrical Engineering at MIT.