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One of the major problems the semiconductor industry faces is the growth in analog/RF and mixed-signal content for systems-on-chip designs, combined with a relatively flat growth in the expertise to supply analog/RF and mixed signal content.

Current approaches for analog and RF design range from those in practice for the past 10 to 20 years, to enhanced and semiautomated versions of those same methods. The current approaches require extensive knowledge of many subjects, including topology, process, computer aided design (CAD) setup, and optimization. Although these methods have shown productivity improvements, they fall short in supplying the analog/mixed-signal content needed to relieve the burden placed on the scarce analog and RF designers.

Geometric programming (GP) based design is a novel approach for quickly creating optimal analog and RF circuits and subsystems according to detailed application specifications. The GP approach models both the circuit and process in a special form that can be solved very efficiently, which results in a globally optimal solution, or conclusively determines infeasibility.

This article looks at standard methods used in today's integrated circuit (IC) design and compares them to the GP-based design approach. It includes examples showing results achieved using this method and comparisons with standard verification techniques, including SPICE simulations and silicon data.

Challenges

Over the last five years, there has been significant growth in the mixed-signal system-on-chip market to keep up with the push to put complex systems, such as cameras and radios, on a single chip. According to the market research firm IBS Group (www.ibsresearch.com), this emerging market is expected to have a very high growth rate, on the order of 40 percent in the next five years. In 2005, it is expected that 75 percent of all silicon-on-chips (SOCs) will contain some analog components. In a recent IBS Group study, it was found that analog accounts for 2 percent of the transistors, 20 percent of the area, 40 percent of the design effort and 50 percent of the design re-spins (FSA). Because of this high demand for analog intellectual property (IP) and a shortage of designers to create it, there is a need for a radically different approach.

Current solutions

I start by looking at current methods for creating analog and mixed-signal designs, and I will review new methods for increasing productivity and some of the challenges they pose.

Figure 1 is a common methodology used to create both analog and mixed-signal circuits.

This methodology is used to create designs ranging from analog building blocks to complex circuits, such as phased locked loops (PLLs). This flow can be broken down into three distinct phases.

Design entry and verification: This is typically accomplished with schematics and SPICE simulation, respectively. The designer will create the design and a test bench with a design kit created by the CAD group. After obtaining a design that meets the design specification, the analog designer will look at noise and run over process, voltage and temperature variations to ensure a robust design.

Physical entry and verification: The layout designer implements the electrical design into its physical representation. Similar to phase one, the designer will use a design kit. Here the goal is to meet the foundry design rules and match the electrical design. In addition, the layout designer must take into account critical layout constraints, which may impact electrical functionality such as symmetry, noise immunity and electro migration.

Final verification: A final verification of the design before sending it to the foundry. The final verification consists of both an electrical and physical validation of the completed design to ensure it meets all performance conditions and foundry design rules. Critical or complete designs will be extracted from the layout and resimulated for a final electrical verification. This is a very time consuming and costly process. Often, errors are found at this late stage, requiring the design and layout to be modified and verified all over again.

Making each phase faster and more efficient will result in incremental improvements, but will fail to address electrical, physical and system level issues at the same time.

The improvements shown in table 1 have reduced design times somewhat, but are still heavily dependant on experienced analog and mixed-signal designers, CAD setup and maintenance, process knowledge, optimization expertise, processing power and a serial flow. The impact is felt greatest in current approaches when specifications are changed late in the design cycle. This causes the design to be compromised or the chip tape-out to be delayed. Both of these significantly impact time to market and competitiveness.

The ideal solution

The following eight items are essential to keep pace with the high demand for analog and mixed-signal circuits, and the shortage of experienced analog and mixed-signal designers.

• Optimal -- application specific customized designs;
• Robust -- ensure performance is met at process, voltage and temperature corners, as well as taking into account noise immunity and parasitics;
• Easy process migration -- moving the design to a new process should be efficient and timely;
• Short design times -- current design times must be reduced by at least 100x;
• Allow exploration of design space -- need the ability to explore boundaries of the design space, as well as understand trade-offs for competing specifications;
• Flexible and scaleable approach -- must provide scalability to allow wide adoption, and flexibility to be applied to all analog/mixed-signal circuitry;
• Expertise level -- experts and novices should be able to use the method to gain knowledge and create analog and RF and mixed-signal designs; and
• Setup and maintenance -- maintenance should be minimum so it does not impact CAD resources and designers' time.

Geometric programming-based design

GP based design addresses all of the above issues and is accomplished through accurately modeling primitive components, such as transistors, to system level attributes, such as jitter. The process variation, parasitics and layout constraints are taken into account and solved at the same time, resulting in a completed analog and RF IP block.

GP architecture

GP based design models both the circuit and process in a special mathematical form known as Geometric Programming. A unique feature of GP is that it models non-linear behavior very well, and because things in nature are typically non-linear, GP fits well into solving these issues. As seen in figure 2, once the process and circuit is modeled in GP, it is submitted to the solver along with the user's specifications and optimized.

The design will result in either a feasible design, which will be globally optimal, or it will be an infeasible design, indicating that not all specifications could be met. Then it will return a sensitivity analysis, which indicates what specifications need to be relaxed to achieve an optimized design.

Modeling the circuit

As a simple example, I will apply this approach to modeling a common source amplifier, shown in figure 3, with an overall objective to minimize power. I will assume values for supply voltage, load capacitance, gain, unity gain bandwidth, and other process parameters. The design variables are length, width, bias current, and resistance.

The n type metal oxide semiconductor (NMOS) device is modeled in posynomial form in terms of its width, length, gate-to-source voltage and drain-to-source voltage. The amplifier is also modeled in posynomial form in terms of the transistor parameters, the load resistance and the bias current. In particular we are interested in modeling the gain, power consumption and bandwidth of the amplifier. The inverse of the gain is given by the posynomial expression,

Formula 1

where RL is the load resistance, gm is the transistor transconductance and gds is the transistor output conductance. The quiescent power is given by the simple monomial expression,

Formula 2

where Ibias is the bias current. Finally, the 3 dB bandwidth is given by,

Formula 3

where CL is the load capacitance and Cout is the total output capacitance of the transistor.

Since all circuit parameters can be expressed in posynomial form, we can write design problems where we minimize gain, given constraints on gain and bandwidth, or problems where we maximize gain, given constraints on power and bandwidth.

Only equations that are affected by a change in the process are the transistor parameters, but not the expressions for gain, bandwidth and power. By modeling the circuit in GP we gain several key advantages:

• Process independent, so once a cell is described in this form, we have the cell for any process. One only needs to update the process parameters to instantiate cells in a new process.
• Circuits expressed in this form can be synthesized very efficiently. Expressing the circuit in GP form lends itself to a special class of optimization problems know as convex optimization. Convex optimization problems can be solved very quickly even for very large circuits. Also, a global minimum is always found or proof of infeasibility.
• Every electrical and physical behavior can be modeled in this form in a very detailed and accurate manner. The description of physical behavior in this form is not part of this article.
• The models are also hierarchical, so they can be reused in other circuits. For example, the amplifier model we described can be used as part of a larger amplifier.

Modeling the process

The next step is to model the process information in GP form. As an example, a metal oxide semiconductor (MOS) transistor is characterized in this special GP form with similar accuracy of a SPICE BSIM3 model. Many parameters are modeled such as gm, gds, Vdsat, and capacitances. Figure 4 compares the GP model to the industry standard BSIM3. In addition to transistors, layout and parasitic information is also modeled.

Synthesizing the design

After the process and circuit are modeled in this special GP form, the design can be synthesized to the designer's specification with a target objective in mind (such as minimize for area, jitter, and/or power). When an optimal design is returned, achieved values along with sensitivities to the objective are returned with a fully routed layout and netlist. If the design is infeasible sensitivities are returned to help guide the user to an optimal design.

GP flow

Figure 5 illustrates the GP flow along with some examples.

Following the seven steps shown, a designer can create analog IP blocks ranging from op-amps to complex blocks such as PLLs and data converters.

As a practical example, we selected an NMOS input folded cascade amplifier in the Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC at www.tsmc.com) .18µm process and swept various parameters such as open-loop gain, input referred noise and phase margin, with an objective to maximize unity gain bandwidth.

The graphs shown in figure 6 are a result of running the trade-off analysis. It took approximately three minutes to complete all three on a 1 GHz workstation.

Additionally, the boundary of the design space and trade-offs for competing performance conditions can be determined in this way because both optimal and infeasible designs are plotted (green indicates optimal designs and red indicates infeasible).

Examples

Now that we have a better understanding of GP-based design, I'll review some practical examples.

Op-amp design. For the first example, I chose an NMOS input current mirror operational amplifier using the TSMC 0.18 um process. This op-amp is well suited for high-speed, low gain applications, and has a higher input referred noise than an equivalent two-stage op-amp because of its inherent lower gain.

It is especially suited for low voltage operation. Our target application is a portable device where we need to minimize power while maintaining a 180 V/us slew rate, 50 dB open-loop gain and 150 MHz bandwidth. The specification and achieved values are shown in table 2 while the topology is shown in figure 6.

I entered the specifications and completed an optimal design in 4 minutes on a single 1 GHz workstation. To ensure a robust design, seven-process/temperature corners were selected and a ±10 percent variation in voltage and ±20 percent variation in on-chip resistance were taken into account.

We retrieved our design including schematics and a fully routed layout (shown in figure 7). We then netlisted the design and ran SPICE simulations over the constraints we defined earlier (seven process corners, variations for voltage and resistance). Finally, we streamed in the GDSII and ran design rules check (DRC) and layout versus schematic (LVS) on the design. The results are shown in table 2.

The target was to obtain the minimum power with the specifications indicated in table 2. As a final check, I ran a trade-off of seven designs to see if I could push the open-loop gain higher. The trade-off showed that jumping to an open-loop gain of 52 dB would increase the power to 2.4 mW and an open-loop gain of 56 dM would be infeasible.

Referring back to the sensitivities of the original design one can see that the unity-gain bandwidth is sensitive to the power objective. This would also be another good candidate to run trade-offs.

PLL design

We have walked through the GP-based flow with a simple op-amp example. Now I will look at a much larger block, a PLL.

The same flow used for the op-amp was again implemented to generate a PLL in the TSMC 0.13 um logic process. Table 3 shows the achieved values through GP design and the corresponding silicon measurements. The complete process from specification to GDSII took approximately 8 hours on a 1 GHz workstation. As can be seen, the method has shown very good correlation to both SPICE simulations and silicon.

Comparison of methods

Tables 4 and 5 compare the current methods available today to the new GP-based approach. As the data shows, tasks that have taken weeks or days can be completed in minutes.

Conclusion

The need for analog and mixed signal content has grown significantly, whereas the methods and expertise has not. A new approach must incorporate robust and optimal designs in a much shorter time than is available today. Additionally, the approach must be scaleable and allow for easy process migration along with minimal CAD support and expertise.

The Geometric Programming design approach addresses these issues and has been validated in silicon for IP building block components, such as pp-amps and LC oscillators, to larger blocks, such as PLLs and data converters.

This approach removes one of the biggest bottlenecks in SOC designs, the analog and mixed-signal components. It also empowers both experienced and novice designers, allowing them to gain knowledge on the process or topology without extensive training or setup. Along with the speed and optimality of the design, the user also gains insight into the design space and the competing objectives, and can make better decisions than would be possible with other currently available methods.

About the Author

Scott Guyton is a technical account manager for Barcelona Design Inc. (www.barcelonadesign.com). Before joining Barcelona, he was an analog and mixed signal application engineering manager for Mentor Graphics Corp. with responsibilities for analog/mixed-signal simulation, layout and verification products.

Guyton has over 15 years of experience in applications engineering and design. He holds a Bachelor of Science degree in electrical engineering from the California Polytechnic State University in San Luis Obispo. Guyton can be reached at scott.guyton@barcelonadesign.com.