The drive to fully integrate communications products onto a single chip has created the urgent need for an integrated RF SoC design flow. Until now the EDA community has not managed to assemble a satisfactory integrated flow for mixed-signal RF because no single vendor has offered all of the necessary technologies. Vendors have tried to use co-simulation to achieve this, but co-simulation seriously complicates the designer's life — even preparing the design for simulation is far more difficult this way and co-simulation is intrinsically slower, less stable and subject to conflicting clock problems.

Even if you have all the technologies, integrating them into a single kernel solution is an enormous task, which engineers have been working on for several years. The good news is that an integrated single kernel solution is now available.

An effective RF SoC flow uses a tightly integrated custom IC design environment, which combines with functional and physical verification tools and foundry-specific design kits to solve the RF SoC problem. Leveraging such a custom IC design environment could reduce the amount of time to simulate an SoC designed, for instance, a wireless modem, from 18 hours to less than one hour.

A typical RF SoC design includes the RF front-end, analog baseband and digital signal processing (DSP) functions. Each block is designed using specific tools. The levels of integration and complexity in RF SoCs require new high-performance and high-capacity tools, in particular, analog and RF simulators.

The proposed RF SoC flow has digital functions handled by a VHDL/Verilog simulator, analog circuits with a SPICE simulator, and RF circuits with a harmonic balance (HB) algorithm. Full-chip verification requires the integration of all these simulation technologies into a single kernel simulator. A typical RF SoC chip is shown in Figure 1.

Analog: In this example an analog simulator combines Newton-Raphson (NR) and one-step-relaxation (OSR) techniques using a unique partitioning algorithm. It groups the circuit into individual strongly coupled node blocks solved using NR iterations, and loosely coupled nodes solved using OSR. As circuit size increases, this algorithm improves the simulator efficiency level and overall simulation speed by allowing different accuracy levels for different parts of the design.

RF: RF designs deal with the frequency domain. Timing simulation is excessively time-consuming and has severe limitations. RF simulators need to combine harmonic balance with Krylov iterative methods to handle multi-GHz signals in modern wireless communication applications. Eldo RF can handle more than 10,000 components of the RF circuitry in the presence of multiple tones.

Analog mixed-signal: SoC designs are characterized by the presence of tightly linked RF and baseband mixed-signal functions. The verification of the complete system requires RF and mixed-signal tool integration. A true mixed-signal simulator must support all standard HDLs: VHDL, VHDL-AMS, Verilog, VerilogA(MS) and SPICE.

Including the RF front-end in a time-domain mixed-signal simulation usually leads to prohibitive CPU times because of the presence of multi-GHz digitally modulated signals. Using time-domain analysis alone is not adequate for the signals used in CDMA or Bluetooth applications. Worse, most communications systems contain tight feedback loops between the RF front-end and baseband systems that include complex DSP functions. Amplifiers with high-speed digital automatic gain control (AGC) are among the simplest examples. Verifying such systems mandates simulation solutions where the RF part can be simulated together with the baseband and DSP parts in an acceptable CPU time.

It is important that a mixed-signal simulator can run in a mode where the modulated steady-state (MODSST) algorithm of the RF simulator is used instead of the regular transient algorithm, to solve the high-speed analog part of the circuit. This architecture radically differs from the so-called “co-simulation” approach where foreign simulators are “glued” together with a cumbersome interface. Rather, it is a straightforward extension to the single-kernel architecture of the mixed-signal simulator, and thus it greatly simplifies the use of the complex simulation algorithms being applied. Simulated time points are chosen to follow the slow-varying baseband information, rather than the fast-varying RF carrier. This results in huge speed improvements over conventional transient simulation. One or two orders of magnitude are common figures when working with the typical baseband-to-carrier frequency ratios in, for example, wireless networks (WLAN) applications. Additionally, designers can mix abstraction levels of different blocks to trade off accuracy or details for speed/performance.

When faced with a large, complex RF SoC project, it makes sense to split the design into separate functional blocks. A proposed segmentation is shown in Figure 2. Each one of these blocks can have their I/O and performance specified such that individual designers can go off and continue with the design of the independent blocks. Usually, for interface purposes, a small functional model of the interface is used, and as the design approaches completion a mixed-mode simulator can be used to verify this interface. Mixed-mode simulators allow the user to run digital logic cells with a digital simulator, while still using a SPICE-level simulator for analog circuitry. Performing functional verification in this way offers significant productivity gains.

Regardless of what type of block is being designed, there is a widely used design flow for IC design. The names of the tools and the file formats may differ, but in general the underlying flow is the same. Design capture, functional verification, physical layout and post-layout verification are the inherent steps.

Once individual block-level specifications have been derived from system-level specifications — noise figures, intercept points, gain, compression points — the RF designer can begin work on the circuit level implementation of the design.

Due to the nature of RF design and a strong dependence on the physical layout, it is essential that the front-end and back-end tools be tightly integrated so that block performance can be verified down to the physical level. Typically, the RF block will have various digital control lines going into it. These will control the power save options, channel selection and other programmable features. In the early stages, this interface can be modeled by using DC sources in the RF simulator to set up various options. Once the digital and RF blocks have been completed, the control logic can be simulated at the same time as the RF circuitry using an RF mixed-signal simulator. The RF mixed-signal design flow is shown in Figure 3.

RF block performance is dependent on the physical layout. Polygon editing layout tools are needed to not only edit the layout, but also increase productivity using device generators and schematic driven layout (SDL). The parameterized device generators create correct-by-construction devices such as MOS transistors, capacitors, resistors and inductors. Inductor layout can be time-consuming, and this is where RF designers in particular can see productivity gains. After placing the components, the interactive or automatic router can be used to route individual nets. With “on-the-fly” feedback of the wire capacitance and resistance, the RF designer can determine the effect of the routing on the design while constructing the layout.

Finally, physical verification and extraction tools can be used to extract parasitics from the layout. The single extraction run can be used to generate a DSPF (detailed standard parasitic format) file for back-annotation onto the design. The DSPF file contains vast quantities of parasitic information. Tools are available today that allow the user to select the nets to which the parasitics should be annotated. Since designers are usually aware of which nets are critical, selecting just these for parasitic back-annotation can significantly cut post-layout simulation times.

To take one example from a company in the cell phone market, the increasing diversity of cellular mobile terminals as well as their enriching feature set places stringent requirements on the efficiency of the whole design process, starting from requirements and ending with the production of ICs and systems. This is especially true as the design time must be shortened and the cost, size and power consumption must be minimized without sacrificing reliability. To meet these requirements, a systematic top-down design method is needed to help to manage the complexity and find globally optimal solutions, along with the importance of a widely accepted mixed-signal multilevel description and modeling language, and the status of the strongest candidate. In addition, the use of a top-down, mixed-signal design methodology, bottom-up IC assembly and verification process, analog IP design outsourcing, as well as design-for-test and test design is crucial to success. Figure 4 highlights the complexities of modern RF SoC chips and the tightly integrated design and verification environment needed to accomplish the goals.

Although the integrated analog flow above imitates a digital top-down methodology, analog design will continue to require handcrafting at the lower level for the foreseeable future. Complete automation of mixed-signal IC design will be impossible until real analog synthesis is available, which is years away. In the medium term, digital and mixed-signal design flows will remain different.

Digital synthesis goes down to the gate level but we don't yet know how to automate directly from analog assumptions down to the generalized transistor level, partly because of the approximations involved. In the analog domain there is a potentially infinite number of solutions for an equation. It will still be up to the engineer to choose the best implementation and tweak the design accordingly. Such a “soft” domain does not suit automation as well as the “hard” binary correctness potential of the digital domain.

However, the integrated single kernel approach described above equips designers with a far more predictable and efficient solution for adding RF functionality to an SoC, especially when combined with design kits and behavioral models for communications components. Figure 5 shows such an integrated AMS SoC verification tool.

By using an integrated, single kernel tool set and progressively building up higher level behavioral models to represent lower level transistor circuits, analog designers can get closer than ever to the benefits of a top-down methodology for mixed-signal design.

Jean Oudinot is the European manager for Mentor Graphics' analog and mixed-signal solutions. He has worked in the EDA industry for the last 25 years, particularly in the analog and mixed-signal simulation area. He was an early promoter for VHLD-AMS standard adoption in 1999 and had been involved in several projects to adopt the new methodology based on the VHLD-AMS standard. Oudinot received his PhD in electronics from Sup Telecomin Paris in 2000 and his master's degree in electronics from the University of Bordeaux in 1977. Based in Meudon-la-Foret (Paris), he can be reached at jean_oudinot@mentor.com.