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With higher levels of integration, the power control loop is tailor-made for the power amplifier chip, which not only yields a robust system, but also makes it easy to implement. The end user can now focus on optimizing the shape of the Vramp signal so it meets the time mask and switching spectrum requirements without the need for continuously modifying the loop parameters or being concerned that it suddenly becomes unstable. The CMOS power control chip used in the first- and second-generation PowerStar power amplifier with intregrated power control modules are knownas being robust over process and temperature. The only drawback is that it requires software compensation of the Vramp signal such that the maximum voltage is less than: Vramp

If this relationship between Vramp and Vbatt is violated, switching transients occur due to an additional phase lag, which prevents the loop of tracking the Vramp sequence on the down ramp. Writing and verifying the various layers of software used in a mobile phone is a time-consuming task, and even the simplest modification could cause a delay of several months in product development. Hence, any software compensation of the power amplifier, if feasible, should be avoided.

First we need to examine the transformation a signal undergoes when passing a “black box” with the impulse response g(t). For any given time continuous signal, the output signal c(t) as a function of the input signal r(t) can be described by the convolution integral as (Eq. 1):

The above equation is not limited in form, i.e., r(t) can be any signal in any given shape.

For the operational amplifier in Figure 2, the same relationship between the input and output is true as long as the input signal remains within boundaries and does not force the output beyond its boundary condition.

The Global System for Mobile Communications (GSM) system is based on time-domain multiple access (TDMA). When switching from receive mode to transmit mode one would have to ramp the output power with a sequence as “smooth” as possible such that the output spectrum in the frequency domains complies with the limits described in the European Telecommunications Standards Institute (ETSI) specification.

The spectral sideband power at +/-400 kHz, when using a raised cosine function as shown in Figure 1, is better than 70 dBc, whereas no shaping profile, i.e., a square wave only yields 10 dBc or worse.

The complex Fourier spectrum of c(t) is defined as:

Ideally, c(t) should reflect the input signal r(t) without being distorted. Thereby, the Fourier spectrum C(ω) is determined only by R(ω). When g(t) differs from a Dirac delta function, the output signal c(t) will be distorted and one would have to compensate the input signal to get the desired amplitude spectrum. As long as g(t) remains unchanged during the burst, r(t) can be determined by taking the inverse convolution of c(t). However, as we shall see, limits in the operational amplifier circuit forces g(t) to change when the proper conditions are met.

The simplified schematic of the CMOS power control loop is shown in Figure 2. The upper limit for Vramp(t) is limited to Vbattmin-Vsd(M6)-Vsgmax(M1)-Vmargin in the input differential stage consisting of M1 and M7, assuming Ve reaches 0 V in steady-state operation. Ve is the differential voltage between the non-inverting and inverting input (M1 and M7) and Vmargin is an arbitrary value chosen to keep M1 and M7 from creating a phase inversion when operated near the gate source voltage threshold.

Since Vbatt minimum is 2.9 V in this example, the maximum level of Vramp before saturation or phase inversion occurs is: 2.9 V-0.3-0.9-0.1= 1.6 V. The Vth is the gate-source threshold voltage. The output voltage Vcc2&3 is limted by Vbatt — Vsd (M12). Previously, the maximum limit for Vramp was defined when Ve was zero, but certain conditions exist where Vε is disallowed from reaching zero.

β, which represents the feedback network, can be calculated as: (R4+R2//R3)/(R4+R2//R3+R7). And the output voltage Vcc2&3 as a function of input voltage Vramp is: Vcc2&3 = (Vramp-Voffset)/β.

For instance, if Vramp is set to 1.5 V, the output voltage Vcc2&3 is 3.5 V. The problem is that Vbatt can decrease to 2.9 while Vramp remains unchanged. Since Vε is no longer zero, the output of M5d and M11d rails to ground + Vdssat to open the channel of M12 until Vε reaches zero. Although M12 is fully saturated, the condition where Vε is zero does not exist unless Vramp is backed off to satisfy Equation 3. Satisfying Equation 3 implies that Vout2 reaches Vbatt-Vsg(M12). The slew rate is then determined by the time it takes to charge the gate capacitance of M12. When Equation 3 is no longer satisfied, the gate voltage of M12 rails to ground in the time it takes to fully charge the gate capacitance. At the output, the voltage remains unchanged until Vε is zero and the time domain response appears to have shifted to the right.

A simulation of the two situations is shown in Figure 3 and 4.

On the trailing edge, the voltage eventually reaches a level where V- is greater than V+. Vout2 now has to charge M12g from zero to Vbatt-Vsg until the V+ terminal equals the V- terminal.

The investigation of the saturation phenomenon resulted in the relationship between Vcc23 and Vramp to meet certain conditions; hence, two solutions can be deduced. The most obvious solution is to measure Vbatt and correspondingly reduce Vramp to satisfy Equation 3, but that would require that Vbatt is being measured in the phone and a digital value is stored in the baseband. A first-order equation can then be added in the software to reduce the digital value of Vramp depending on Vbatt prior to initialization of the burst. However, as previously mentioned, the resources in the software department are often limited and a digital implementation seems less attractive as long as other solutions are available. The other solution is to implement a second feedback loop that automatically preserves the linearity of M12. Implementing a second feedback loop raises the concern of stability issues and leaves only two choices when setting the bandwidth. Either it needs to be faster and in-lock prior to or at the same time as the master feedback loop, or it has to be much slower.

A slow feedback loop could be detrimental because the correction occurs during the burst, and such a change could lead to group delay.

The idea is to detect the voltage differential between the source and gate of M12. The differential voltage is then compared with a known reference. If the non-inverting input (V+) of U1 exceeds the inverting input (V-), the output rises linearly as a function of (V+ - V-) (-k), where k is the gain. The output error voltage is then subtracted from Vramp until equilibrium is obtained.

Operating the feedback loop in a non-saturated mode forces the output error voltage from U2 to approach 0 V. Practical implementation of U2, despite using known techniques, does not allow Vout of U2 to go to L when considering process variations. Here, L represents the minimum achievable voltage above ground. Due to the architecture of the power amplifier, achieving an output power of 0 dBm requires a Vramp voltage of approximately 300 mV and the differential change in output power is approximately 0.25 dB/mV. Assuming that the CMOS process variation allows Vout of U2 to be less than 10 mV, the error in output power is still significant. Instead of using pure voltage summation between Vramp and the error voltage, U2 can successfully convert the differential voltage into a current sink, which then is being used to drop the voltage across a resistor. It benefits from the off state having zero current flowing through the resistor. Only the leakage current contributes to an error in output power due to process variations.

The two circuit topologies in Figure 6 and Figure 7 are only useful as long as Vth of M1 remains unchanged with process. Since Vth is not as well defined as Vbe, any variation in Vth is directly transferred to an error voltage across R5. Furthermore, using an operational amplifier limits the bandwidth of the feedback loop. Eliminating the uncertainty in Vth and increasing the bandwidth is achieved by adding a positive field-effect transistor (PFET) transistor with the same L and W properties as M1. (Figure 8.)

When Vsg declines below the threshold voltage, M3 becomes active and allows current to flow through the current mirror consisting of M4 and M2. The output voltage Vcc2&3 is then diminished until equilibrium is reached by reducing the voltage on the inverting input of U1.

This prevents the gate voltage of M1 to rail to ground and effectively eliminates any phase lag in the loop due to saturation. Although the time domain signal is being compressed from its original level, the improvement is adequate to prevent excessive switching transients from being generated (Figure 9).

The disadvantage of connecting the source of M3 to the power supply (Vbatt) is that any ripple on the power supply is transferred onto Vramp and the power supply rejection ratio degrades substantially. Furthermore the output impedance of the current sink M2 is insufficient.

Summing the current from the current mirror with a fixed current source forms a cascode-coupled current sink as shown in Figure 10. The output resistance is approximately gm*Rds^2. Less gain in the feedback loop is needed to obtain an appropriate error voltage across R5, thereby allowing M21 to be slightly saturated while maintaining a satisfactory switching transient performance. The voltage drop across M12 diminishes to 50 mV instead of 100 mV when using the cascode coupled feedback loop. Figure 10 also shows the implementation of the cascode-coupled current sink consisting of M14, M15, M16, M17 and M18.

The output voltage VCC23 is converted into power and upsampled to 1.2 MHz. Ideally, the simulation is performed with a carrier of 900 MHz or 1800 MHz, but to make a fast Fourier transform (FFT) on the power spectrum, the time step ceiling has to be well below the smallest time duration of the sinusoidal carrier wave. Therefore, 1.2 MHz was chosen, which allows analyses of the most critical frequencies such as +/-400 kHz, +/- 600 kHz, etc.

Measurements indicate that without any phase lag prevention, the switching transients +/- 400 kHz from the carrier on the down ramp is -14 dBm in the worst case (the limit according to the ETSI specification is -19 dBm). Inhibiting the phase lag leaves a margin of -19-(-14-11.5) = 5 dB.

Only rated power and efficiency matters. Although the maximum power and peak efficiency look good on paper, they cannot be achieved in practice. Therefore, it is important to minimize any headroom in output power required to meet performance over all conditions.

The circuit topology chosen for the third-generation GMSK/enhanced data for GSM evolution (GMSK/EDGE) power control is simple, yet effective. Measurements on the RF3166 have shown that switching transients are met over all conditions and there is no need for additional power headroom. The impact on peak efficiency for this design is approximately 2%, but the benefits of not having a need for additional power headroom allows the phone designer to operate at a higher power compared to previous products.

Ulrik Riis Madsen received his B.S.C. with honors in electrical engineering from HIBAT, Denmark in June 1996 with major area in analog/digital control systems and high-frequency amplifiers. Until October 1999, he was employed with Dancall Telecom in Denmark and designed the transmitter used in various mobile phones. He joined RF Micro Devices® in 1999 and has designed several key power amplifier modules and also conceptualized the PowerStar® concept. Madsen is currently a staff engineer in the corporate research and development group with RF Micro Devices^™.