To accelerate the development of high-performance infrastructures for 3G and next-generation 4G systems, Analog Devices Inc. has readied high-speed data converters with low power consumption at faster conversion rates. While the AD9779 is a dual 16-bit high- performance, high-frequency digital-to-analog converter (DAC), the AD9444 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, track-and-hold circuit, optimized for power, small size, and ease of use (see the figure). Presently, AD9779 is in sampling mode and AD9444 in production. The AD9779 is expected to go into production phase next month.

The AD9779 provides a sample rate of 1 Gsps, permitting multicarrier generation up to its Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the AD8349. Consequently, when paired with AD8349, it provides a baseband to RF transmit solution while still meeting transmit spectral mask requirements. A serial peripheral interface (SPI) provides for programming many internal parameters and also enables read-back of status registers. The output current can be programmed over a range of 10 mA to 30 mA.

Based on an advanced 0.18 µm CMOS process, the DAC features ultralow noise and intermodulation distortion (IMD) to enable high-quality synthesis of wideband signals from baseband to high intermediate frequencies. Thus, spurious free dynamic range (SFDR) at 70 MHz output frequency is given at 88 dBc, and IMD is -92 dBc. Other features at 70 MHz output include noise spectral density of -161 dBm/Hz and ACLR of 77 dBc. Single-ended CMOS interface supports a maximum input rate of 300 Msps with 1x interpolation. The AD9779 operates from 1.8 V and 3.3 V supplies for a total power consumption of 325 mW. It is supplied in a 100-lead QFP package. The current outputs of the AD9779 can be easily configured for various single-ended or differential circuit topologies.

Likewise, the 0.35 µm biCMOS-based 14-bit AD9444 offers about 5 dB to 7 dB improvement in SFDR over currently available ADCs. As a result, the AD9444 features a SFDR of 97 dBc at 70 MHz input frequency with excellent linearity. Its differential non-linearity (DNL) performance is rated at ±0.3 LSB and integral non-linearity (INL) is ±1.0 LSB. The ADC operates at up to an 80 Msps conversion rate and is optimized for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. Its analog bandwidth is given at 650 MHz. The ADC requires 3.3 V and 5.0 V power supplies and a low-voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI-644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances. Typical power dissipation is 1.2 Watts.

Optional features allow users to implement various selectable operating conditions, including data format select and output data mode. The AD9444 is available in a 100-lead surface-mount plastic TQFP/EP package specified over the industrial temperature range (40° C to +85° C).

For more information, visit www.analog.com.