Combining 0.18 µm CMOS process with patent-pending switch current array, designers at Analog Devices have developed an unmatched 14-bit digital-to-analog converter (DAC) that has broken the 1 Gsample per second (Gsps) barrier. At 1.2 Gsps, the AD9736 sets a new data rate benchmark, while still providing superb dynamic range and good power efficiency, claims the manufacturer. It is designed for wider synthesis bandwidth and higher IF generation in instrumentation, communications and military applications.

The 14-bit AD9736 provides a fast low-voltage differential signaling (LVDS) input interface, which enables high conversion rates over a wide bandwidth. This allows it to receive data at a high speed, while maintaining low distortion and noise, simplifying the transmit signal chain and enabling high-quality synthesis of wideband signals at IF frequencies up to the Nyquist rate. In addition, the high-speed 14-bit DAC is optimized for low power consumption to deliver significant improvement in speed, power and performance.

To double the incoming sample rate from ASICs or FPGAs capable of operating at up to 840 Msps, the AD9736 features a 2X digital interpolation filter. This allows users to take full advantage of the data converter's sample rate with existing digital technology, while future-proofing the design. A novel clock-to-data synchronization scheme simplifies the interface timing and enables the extreme sample rate to be realized.

Some key performance specs include intermodulation distortion (IMD) of -74 dBc at an output frequency of 255 MHz and better than -65 dBc up to a 600 MHz output frequency. While spurious free dynamic range (SFDR) is 63 dBc at a 300 MHz output frequency and 53 dBc at 600 MHz, sampling at 1.2 Gsps, the DAC's noise performance is excellent, with noise spectral density of -158 dBm/Hz synthesizing a 300 MHz output. Besides high noise performance, its power consumption is substantially lower than existing 14-bit devices. The total power consumption is 380 mW at 1.2 Gsps with the interpolation filter bypassed and 550 mW with the interpolation filter enabled.

Like all high-speed DACs from ADI, conversion in the AD9736 is initiated on the rising edge of each input clock at the full DAC sample rate. Sampling only on the rising clock edge eliminates potential performance problems related to clock duty cycle sensitivity. According to the supplier, DACs that sample on both rising and falling clock edges can exhibit feedthrough of the half-rate clock if a nearly perfect 50% duty cycle is not maintained. Even small variations in duty cycle can create a significant half-rate spur and images that degrade SFDR performance over the Nyquist bandwidth. The AD9736 clocking architecture renders it largely insensitive to clock duty cycle variations.

Supporting a double data rate (DDR) mode, the converter includes a serial port interface (SPI) that provides for programming many internal parameters and also enables read-back of status registers. Implemented in 0.18 mm CMOS process, the AD9736 uses dual supplies — 1.8 V for digital and 3.3 V for analog functions. The DAC's output currents can be programmed over a range of 10 mA to 30 mA and can be easily configured for various single-ended or differential circuit topologies.

Sampling now, the AD9736 will be in production in the fourth quarter. It is offered in 800 Msps and 1.2 Gsps speed grades. For reduced package parasitics, it is housed in a 160-pin ball grid array (BGA) package. In 1000-piece quantities the AD9736-1200 is priced at $59.50.
Analog Devices Inc.
(781) 937-1428
www.analog.com/AD9736