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Frequency converters are an important part of most RF front-ends. As there are no ADCs with several bits that can process information at GHz frequencies, the frequency downconverter circuit plays a decisive role on every receiver. Besides, the implementation of a direct conversion topology to baseband or low IF allows an optimal integration due to the reduction in the use of discrete components. In Figure 1, a block diagram of the direct conversion topology can be seen. The integrated components presented in this article are gray shaded and marked with a dotted line.

As seen in Figure 1, a mixer, which is active and based on the Gilbert cell, and a differential cross-coupled oscillator with integrated LC tank form the presented downconverter circuit.

Of course, frequency conversion must be done without introducing noise or degrading the signal, thus, there are two important specifications in the performance of the downconverter circuit: the oscillator should have low phase noise and the mixer should present high linearity. Besides, if the oscillator phase noise fulfills the requirements of DCS-1800, it is verified that there will not be inter-channel interferences.

To improve the phase noise of the oscillator, a good quality factor tank circuit was designed¹. A balanced inductor and two PN junction varactors form this tank circuit. The way to improve the linearity of the Gilbert cell mixer without too much degradation in conversion gain and noise figure is to use a class-AB input stage².

Although the technology used to implement the circuits is a 0.8 µm SiGe, the oscillator was integrated with only MOS transistors, as will be explained later. On the other hand, the mixer was designed with HBT transistors, except for the current source, which has been implemented with MOS transistors.

As explained below, the configuration used is a differential cross-coupled with integrated LC tank. The oscillator's schematic is shown in Figure 2.

The first remarkable characteristic of the oscillator is that it was implemented with MOS transistors. The limitations of the technology made impossible the use of HBT transistors due to their low base-emitter breakdown voltage, which was approximately 1 V. This implies that the maximum output power of the oscillator is around -6 dBm³.

As mentioned in N. Rodriguez's 2002 Ph.D. dissertation, “Mezcladores Integrados en Tecnologías SiGe y BiCMOS para Frecuencias inferiores a 1.8 GHz⁴,” Gilbert-cell-based active mixers in the technology have an optimum performance with a LO power around 0 dBm. As it is impossible to obtain such output power using HBT transistors, it was decided to design the VCO with MOS transistors, even though MOS transistors include higher high-frequency noise.

After selecting a MOS topology, among the possible architectures that employ these transistors, the cross-coupled CMOS was selected due to its best ratio between phase noise and power consumption when working in the current limited region^5,6. It will be demonstrated that with this architecture, a proper design of the tank allows fulfilling the restrictive DCS-1800 phase noise requirements without an excessive increase in power consumption.

Moreover, two tail capacitors were added in parallel with the biasing current source because their presence can improve the phase noise of the oscillator⁶. Simulations show that, not only is the phase noise improved, but the output power is also increased with an insignificant reduction of the oscillation frequency.

To select the value of these capacitors, there is a trade-off between the improvement in phase noise and output power, the sensitivity of the oscillator to supply voltage variations⁶, and the occupied area.

Since, as derived from the Leeson model¹, the VCO phase noise performance depends highly on the quality factor of the tank circuit, it is necessary to design passive elements with quality factors as high as possible.

Due to the fact that at the frequency of interest (1.8 GHz) inductors usually dominate the quality of the tank¹, this section will emphasize the design of the inductor. To design a differential oscillator, the inductor configuration must fulfill the symmetry requirements. Thus, the choice must be made between the use of two standard inductors symmetrically placed, or a balanced inductor.

The standard technology used includes a highly conductive P-type substrate, thus, substrate losses will have an important effect in the quality of the inductor.

The way to decrease these losses is to reduce the inductor's area. A balanced configuration was selected for the inductor because balanced inductors present more coupling effects between their turns. Thus, a bigger inductance can be obtained using the same area with two symmetrically placed standard inductors, so substrate losses will be reduced. Furthermore this inductance is obtained with less metal length, and the inductor's resistance is lower than one in a standard inductor^3,7.

An additional advantage that comes from using a balanced inductor is avoiding the parasitic coupling that occurs between the two inductors symmetrically placed.

As explained before, substrate losses will be important, affecting the quality of the inductor, however, resistive losses are as much important as substrate losses.

To reduce these ohmic losses, two improvements were made. The first was to connect, in parallel (except in the underpasses), the two available metal layers to diminish the series resistance of the coil. The second was to design the spiral hollow to avoid the high resistance of the inner turns due to proximity effect¹.

The geometrical characteristics of the designed balanced inductor are presented in Table 1 and a microphotograph is shown in Figure 3. As seen in Figure 5, at the frequency of interest, it has an inductance of around 2.15 nH, with a quality factor of 7.6.

The second element in the tank circuit is the varactor. In this particular case, the integrated varactor is based on the variable capacitance that appears in a P-N junction when it is reverse biased. The varactor consists of P+ islands diffused in an N-well and surrounded by a N+ zone. In this way, the depletion zone appears around all of the P+ diffusion so the capacitance is higher, which explains the capacitance variation⁸.

To increase the varactor quality, some improvements were made:

• N+ contacts have been included in the N-well because they are useful to decrease the series resistance of the device.
• The distance between P+ and N+ diffusions was reduced to the minimum. This way, the N-well resistance is decreased. Being this minimum distance of 1 µm higher than the maximum length of the depletion zone, the avalanche breakdown is avoided⁸.
• The P+ islands are square and have the minimum side length allowed by the technology. This way the series resistance of the varactor can be minimized⁹.
• Another important parameter is the width of the metal track that connects diffusions of the same type. If this width is increased, the resistance of the track will be decreased but the parasitic capacitance will increase and the auto-resonance frequency will decrease. Simulations give a trade-off solution of 1.2 µm⁸.
• Finally, a N+ buried layer was included under the N-well zone to provide a low impedance way for the current⁸.

The geometrical characteristics of the varactor are presented in Table 2 and a microphotograph is shown in Figure 4. As seen in Figure 6, at the frequency of interest, it has a capacitance variation between 3 pF and 5 pF with a quality factor between 35 and 60.

The measurement system used for the characterization of the passive elements consists of the Hewlett Packard Co. (www.hp.com) HP8719ES vector network analyzer and the Cascade Microtech Inc. (www.cascademicrotech.com) ACP40 GSG microprobes. To calibrate the measurement system the SOLT method was used. Finally, the Four Step De-embedding Method¹⁰ was used to remove the parasitic effects introduced by the measurement structures.

The measured results of the passive elements are presented in Figure 5 and Figure 6.

Once the passive components are measured and characterized, using Equation 1, the equivalent conductance of the tank can be calculated, as seen in Figure 7a.

The negative conductance generated by the CMOS oscillator active circuit can be obtained as a first approximation, as seen in Equation 2. It can be calculated as a much more complex and accurate expression taking into account the parasitic capacitances and the channel admittance of the transistors⁸.

Knowing the equivalent conductance of the tank, the transconductance for each of the transistors of the active circuit can be obtained. It is normal to include a security factor around 2 or 3 in the negative conductance of the active circuit¹. As the transconductance of a transistor can be approximately obtained with Equation 2, it can be seen that there is a trade-off between an increase in the tail current (and, thus, in the power consumption) and an increase in the transistor width (and, thus, a decrease in the oscillation frequency and the gain at high frequencies).

Once the tank circuit is modeled and the active circuit is designed, the phase noise can be calculated. With Equation 3, an approximation to the phase noise of the oscillator can be obtained¹.

With this equation, the estimated phase noise of the oscillator at 100 kHz from a 1.8 GHz carrier is -107.9 dBc/Hz.

The downconversion mixer operates in the direct conversion receiver presented in Figure 1 with the signal from the LNA. To avoid intermodulation problems due to unwanted signals, the mixer should present as high a linearity as possible.

The gain of the LNA is high so the noise figure of the mixer is not a critical parameter. Besides, the conversion gain of the mixer must be high enough to compensate for the loss of the filters that come after it. The linearity improvement usually implies a worsening in the gain and noise figure of the circuit⁴. Then it becomes necessary to reach a trade-off solution between linearity, gain and noise figure.

The most widely used downconversion mixer is the Gilbert cell¹¹, which, being active, has enough conversion gain, but is not linear enough for our application. The only way to achieve acceptable levels of gain and linearity in a Gilbert cell is to turn the standard RF input stage into a class-AB stage with resistive degeneration⁴. The schematic of this mixer is shown in Figure 8.

The mixer presented in Figure 8 was designed with SiGe HBTs because of their gain. However, the current source was implemented with MOS transistors due to their better noise and stability characteristics.

Equation 4 represents the conversion gain of the mixer, where V_T is the thermal voltage and R_OUT is the mixer's output resistance. As the gain depends on the transconductance of the input transistors (M₁, M₂ or M₃) it depends on the bias current of each branch (I₁ or I₂).

Equation 5 represents the noise of the mixer, where r_b is the base resistance of the transistors, Z_S is the source impedance, and β(ω) is the transistor's current gain, which is frequency dependent.

The first term represents the contribution of thermal noise to the total noise; the second and third terms represent the contribution of collector and base currents shot noise, respectively.

The way to decrease the noise of the mixer is to decrease the base resistance, increasing the area of the input transistors. To further reduce this resistance, the transistors used have double base contact. Also, an increase in the bias current improves the noise, but it has one disadvantage, which is that the input impedance matching becomes worse⁴.

The RF and IF ports must be matched to 50Ω. The output matching is achieved by placing two series resistors (R_S1 and R_S2). The input matching is obtained with a trade-off between the biasing current, the input transistor's width, and the degenerative resistor's values².

To avoid degrading linearity, the LO power level must guarantee the appropriate switching performance in the mixer core. In this design, mixer LO power level is close to 0 dBm.

Due to this quite high value, the isolation between the LO input and the IF output must be high to avoid feed-through and interference problems. To suppress the LO signal at the IF output, the differential Gilbert cell was used. In addition, other ways of increasing LO-IF isolation, maximizing the layout symmetry, or using common centroid techniques have been used.

Once the oscillator and the mixer have been designed, the final step to implement the downconverter circuit is to lay them out together.

The microphotograph of the downconverter circuit is presented in Figure 9. The chip area is about 1900 × 700 µm2. In the layout, some capacitors between the DC voltage pads and ground were added to stabilize the supply voltage, eliminating the high frequency variations in this voltage, which can adversely affect the circuit response.

Another consideration is that several substrate contacts connected to the ground pad were added around the transistors to provide a stable substrate voltage. Finally, the layout was designed with the maximum symmetry to reduce the phase noise of the oscillator⁶ and increase the LO-IF isolation.

As seen in Figure 9, between the oscillator and the mixer two pads were included. This is to fill the need of feeding back the oscillator's output signal to the loop of the PLL. Moreover, two series capacitors have been included to isolate the oscillators' output DC level from the input of the mixer.

There is another important characteristic that must be taken into account — the parasitic resistance introduced by the metal tracks that connect the passive elements of the tank circuit with the active circuit.

In Figure 10, the phase noise variation — when the parasitic resistance of the metal tracks increases the inductor or varactor resistance — is presented. The biggest phase noise variation occurs when the inductor's resistance increases, so special care must be taken when designing the connections of the inductor.

To minimize the resistance of the metal tracks, the two metal layers connected in parallel were used. The track width must be a trade-off between the parasitic resistance, which increases the phase noise, and the parasitic capacitance, which decreases the output frequency and tuning range.

The downconverter circuit's response was measured with the HP E4407B spectrum analyzer. For the supply and control voltages, the Cascade Microtech DCQ-05 PPGPP and ACP40 GSG microprobes were used. The supply voltages of the mixer and the oscillator are independent. For the input RF and output IF signals, the Cascade ACP40 SGS microprobes were employed.

The measurement of the phase noise response of the VCO at a frequency of 1.8 GHz is presented in Figure 11. This measurement was done for a core current of 8 mA, and the optimum performance of the oscillator was obtained with it. With this current, the oscillator is operating in the current-limited region, but near the limit of the voltage-limited region⁶.

As seen in Figure 11, the measured phase noise at 100 kHz offset from the 1.8 GHz carrier is -103.8 dBc/Hz. As it can be observed, the previously calculated approximation -107.9 dBc/Hz is good, but optimistic because it gives a value around 4 dB better than the real phase noise. This difference can be attributed to the parasitic resistance of the metal tracks, which connect the passive elements of the tank circuit.

The whole downconverter circuit's measurements were done with the same current of 8 mA in the oscillator's core. Figure 12 shows the mixers output frequency variation when the voltage is applied to the varactor changes.

As seen in Figure 12, there are two biasing points where the output frequency is 36 MHz: f_IN - f_LO when f_LO < f_IN and f_LO - f_IN when f_LO > f_IN.

Measurements show that the phase noise response, and the rest of the mixer characteristics, are worse when f_LO > f_IN, so all the following measurement results have been obtained with a control voltage of 4.5 V. These results are presented in Table 3.

As seen in Table 3, the design goals were achieved. The gain is not very high, but enough to compensate for the loss of the low IF filters. The noise figure is relatively high, but as the LNA has high gain, this result is acceptable. The IP3 is high enough for our application and higher than the one of a standard Gilbert cell. Finally, the input and output matching is good.

A fully integrated core low power consumption VCO, which achieves the restrictive phase noise specification for DCS-1800, was designed. The measured phase noise is -103.8 dBc/Hz at a 100 kHz offset from a 1.8 GHz carrier.

The oscillator was designed using 0.8 µm MOS transistors. The ability of the CMOS technology to achieve good phase noise results, if a proper LC tank is designed, was demonstrated.

It was also demonstrated that a careful design allows obtaining mixers based on Gilbert cells with enough conversion gain and linearity. A class-AB input stage should be used to improve the linearity. After laying the oscillator and the mixer out together, the resultant downconversion circuit fulfills the specifications of a baseband or low IF direct conversion receiver for DCS-1800.

1. J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design (Kluwer Academic Publishers 1998).

2. B. Gilbert, “The Micromixer: A Highly Linear Variant of the Gilbert Mixer Using A Bisymmetric Class-AB Input Stage,” IEEE Journal of Solid-State Circuits, vol. 32, No. 9, pp. 1412-1423, September 1997.

3. J. Aguilera, “High Quality Factor Integrated Inductors in a standard 0.8 µm SiGe technology”, Ph.D. Dissertation, University of Navarra, Spain, 2002.

4. N. Rodriguez, “Mezcladores Integrados en Tecnologías SiGe y BiCMOS para Frecuencias inferiores a 1.8 GHz,” Ph.D. Dissertation, University of Navarra, Spain, 2002.

5. J. Hernández, H. Hein, F. Oehler, and A. García-Alonso, “Analysis of Architectures for 1.8 GHz CMOS LC-tank Voltage-Controlled Oscillators,” XIV Design of Circuits and Integrated Systems Conference, pp. 137-142, November 16-19, 1999.

6. A. Hajimiri and T.H. Lee, “The Design of Low Noise Oscillators” (Kluwer Academic Publishers 1999).

7. A.M. Niknejad, R.G. Meyer, and J.L. Tham, “Fully-Integrated Low Phase Noise Bipolar Differential VCOs at 2.9 and 4.4 GHz,” Proceedings of the 25th European Solid-State Circuits Conference, pp. 198-201, 1999.

8. E. Hernández, “Integration of a Frequency Converter for TV Applications in 0.8 µm SiGe Technology,” Ph.D. Dissertation, University of Navarra, Spain, 2002.

9. E. Pedersen, “RF CMOS Varactors for Wireless Applications,” Ph.D. Dissertation, Aalborg, Denmark, 2001.

10. T.E. Kolding, “On wafer Calibration Techniques for Giga-Hertz CMOS Measurements,” Proceedings of IEEE International Conference on Microelectronic Test Structures (ICMTS), pp. 105-110, March 1999.

11. B. Gilbert, “Current-mode circuits from a translinear viewpoint: A Tutorial,” Analog IC Design: The Current Mode Approach, Eds. London IEE, Cap. 2, pp 11-91, April 1990.

E. Hernández received the B.S. and M.S. degrees in electronic engineering from ESI of Navarra University in 1999. He also joined the TECNUN's RF integrated circuit design group, San Sebastian, Spain, in 1999. Hernandez obtained his Ph.D. degree in monolithic voltage controlled oscillators for RF applications in December 2002, then joined the Gipuzkoa Center for Technical Research (CEIT) as an associate researcher. His main interests also include the design and characterization of passive components and mixers in standard low cost technologies. He can be reached at ehernandez@ceit.es.

R. Berenguer received the B.S. and M.S. degrees in electrical engineering from ESI of Navarra University in 1996. In 1999, he joined CEIT as an associate researcher. He received his Ph.D. in 2000. His research interests include CMOS and BiCMOS RF circuit design for low cost and highly integrated front-ends. He can be reached at rberenguer@ceit.es.

J. Meléndez received his M.S.E.E. degree in 1998 and his Ph.D. degree in industrial engineering in 2002 from Universidad de Navarra. He researched the development of a low power CMOS Low IF digitization GPS front end. His current research interests include system design level of RF transceivers for domotic applications and VCO development for WLAN applications in SiGe technology. He can be reached at jmelendez@ceit.es.

N. Rodríguez received her M.S. degree in telecommunication engineering in 1998 from UPNA (Pamplona-Spain) and her Ph.D. degree in industrial engineering in 2002 from Tecnun, University of Navarra, San Sebastian-Spain. As part of her research work, she designed active and passive mixers in CMOS, BiCMOS and SiGe technologies for RF front-ends. Her current research interests include the integration of SiGe and CMOS devices into RF receivers for WLAN applications. She can be reached at nrodriguez@tecnun.es.

J. Aguilera received his B.S. and M.S. degrees in electronic engineering from ESI of Navarra University in 1999. He joined ESI as associate researcher in 199, as well. In March 2002 he joined CEIT and received his Ph.D. in April. His work involves improving the quality of integrated inductors for RF applications from the geometrical design point of view. He has also worked in several RF projects for Infineon Technologies AG, Austriamicrosystems AG and Xignal Technologies AG. In December 2002, he joined Modis International to work for Philips Research labs in Eindhoven, the Netherlands. He is currently working in the implementation of a software for RFIC optimization in Philips IC design flow. He can be reached at aguilera@natlab.research.philips.com.