Radio link range is a key performance parameter in cost-sensitive WLAN systems targeted for the consumer market. As transmitter output power is limited by government regulations, receiver sensitivity is of prime importance. The receiver's low noise amplifier block dominates the receiver's noise figure.

A high-performance, low-cost, highly repeatable two-stage low noise amplifier (LNA) for use in 5 GHz to 6 GHz wireless applications is presented. The LNA makes use of standard, low-cost FR4 board material, inexpensive 0402 case-size chip components, and new, cost-effective silicon-germanium (SiGe) transistors in standard surface-mount packages. Gain in excess of 20 dB is achieved with 1.5 dB noise figure in a design consuming 16 mA at 3.3 Volts, while requiring 80 mm² of PC board area. A discrete transistor design provides design flexibility while allowing for fast time-to-market.

Despite the ongoing trend toward higher integration levels, discrete RF components still have their place in contemporary wireless designs. While component vendors for more mature market segments, such as cellular and personal communication system (PCS), offer a wide range of proven, cost-effective and highly integrated devices, RF designers tasked with bringing product quickly to market at higher frequencies in new, emerging areas have fewer choices available in terms of fully integrated components.

Furthermore, early generation integrated devices for such emerging markets often exhibit poor performance. Discrete RF devices offer advantages such as superior performance, tremendous design flexibility and versatility, faster time-to-market, low cost and reduced risk.

Silicon- and silicon-germanium (SiGe) based transistors and monolithic microwave integrated circuits (MMICs) have demonstrated tremendous improvements in both performance and cost, and are steadily expanding into areas that previously were only served by more expensive gallium arsenide (GaAs) based devices.

The final product used throughout this article is Infineon Technologies AG's (www.infineon.com) BFP640 silicon germanium RF transistor, which is shown in a two-stage LNA application targeted for WLANs and other systems using the 5 GHz to 6 GHz frequency range.

Figure 2 shows Infineon's current SiGe transistor family, and Figure 6 and Figure 7 give a schematic diagram and bill of material (BOM) for the LNA.

Measurement results are presented in Table 1. These results are mean values taken from a sample lot of 12 circuit boards. Please note that the reference planes for all measurement data shown in Table 1 are at the PC board's SMA RF connectors — in other words, if losses at the LNA input were subtracted, the noise figure values would be slightly lower than shown.

The BFP640 is a SiGe heterojunction bipolar transistor, manufactured in a B7HF process, is a derivative of Infineon's original SiGe transistor, the BFP620.

In the BFP640, a lower or “lighter” dopant concentration in the transistor's collector region is used. The lighter collector doping increases the minimum collector-emitter breakdown voltage (V_CEO), reduces the transistor's internal parasitic collector-base capacitance (C_CB), and reduces undesired internal feedback, yielding increased gain and improved stability margin. See Figure 1.

The higher minimum breakdown voltage (4.0 V V_CEO, versus 2.3 V for the BFP620) makes operation in 3 volt systems more convenient, as it is not possible to exceed the transistor's maximum collector-emitter voltage in a system using a 3 volt power supply.

The higher breakdown voltage permits the elimination of circuit elements previously needed to reduce the 3 volt system supply voltage to below 2.3 volts, which were required for safe operation with the older transistor. In addition to being useful in LNA applications, the new transistor has been successfully employed as a power amplifier (PA) driver in 5 GHz WLAN designs.

The BFP640's two siblings, the BFP650 and BFP690, utilize the same process enhancements as the BFP640, but have larger emitter areas, allowing for increased collector current and higher RF output power levels. The maximum ratings for the BFP640, BFP650 and BFP690 are given in Table 2. A chart showing details of Infineon's new SiGe transistor is given in Figure 2.

The LNA consists of two identical BFP640 stages in cascade. All RF simulations and printed circuit board design steps took place within Eagleware Corp.'s (www.eagleware.com) Genesys version 8.0 software design package.

Effort was made to minimize noise figure as well as the number of external matching elements required. The circuit board is laid out in such a manner as to permit easy testing of either stage individually. Lumped element matching techniques are used exclusively to minimize required PC Board area.

In general, for a linear two-port device characterized by S-parameters, the two necessary and sufficient conditions to guarantee unconditional stability (meaning no possibility of oscillation when the input and output of the device are both terminated in any passive real impedance) are:

(a) K > 1 and (b) |Δ| < 1

where

K = 1-|s11|² -|s22|² +|Δ|²/2|s12 • s21|

|Δ| = |s11 • s22 - s12 • s21|

In the literature, one may encounter an alternative form for these two conditions, as:

(a) K > 1 and (b) B₁ > 0

where

B₁ = 1+|s11|² -|s22|² -|Δ|²

A single stage of the two-stage LNA was measured for S-parameters from 125 MHz to 2 GHz, and then from 2 GHz to 15 GHz. The S-parameter files from each measurement were imported into the Genesys package.

Genesys was employed to calculate and plot stability factor K and stability measure B1 in each case. See Figure 3 and Figure 4.

One can see K > 1 and B₁ > 0, showing that the necessary and sufficient conditions for unconditional stability have been met. Since both stages are of identical design and layout, it is sufficient to check for unconditional stability of either one of the two stages.

If the criteria for unconditional stability are satisfied for a single stage, then an additional identical stage may be safely cascaded after the first stage, provided the two stages don't have an undesired feedback path between them.

In other words, unless the individual unconditionally stable stages can “talk” to each other via leakage paths through shared DC supply lines or other PC board features, cascading individual unconditionally stable stages will result in an unconditionally stable multi-stage amplifier.

In making stability calculations using measured S-parameters, one must bear in mind that the reverse transmission coefficient (S12) of high-transition frequency devices like the BFP640 becomes vanishingly small at lower frequencies. Therefore, the signal being measured may well fall into the noise floor of the network analyzer being used. It's important that network analyzer dynamic range considerations are taken into account when making the S-parameter measurements. Otherwise, the measured S-parameter results may be suspect, and one may not get a “clean curve” when plotting K and B1 — particularly for frequencies below 1 GHz. An excellent reference for the interested reader is given in Agilent Technologies Inc.'s (www.Agilent.com) application note 1363-1, “Understanding and Improving Network Analyzer Dynamic Range.”¹.

This LNA makes use of a “trick” to enhance third-order intercept performance.

In brief, a relatively large-value capacitor is placed across the base-emitter and collector-emitter junctions to provide a low impedance path at low frequencies. This low-frequency path serves to bypass the low-frequency difference product (f₂-f₁) resulting from a two-tone test. (See the schematic diagram in Figure 6. C3, C8, C6 and C11 perform this function).

The rule of thumb states that there exists approximately 10 dB difference between the amplifier compression point and the third-order intercept point. Use of this “trick” gets around this general rule, and increases the difference from the expected 10 dB to between 15 dB and 20 dB. Employment of this technique is why the LNA's input third-order intercept point (IIP₃) of +5.0 dBm is more than 10 dB higher than the amplifier's typical input 1dB compression point (IP_1dB) of -14 dBm. For additional detail on how this capacitor trick works, please refer to Infineon's application note AN060, “A High IIP3 Low Noise Amplifier for 1900 MHz Applications Using the SiGe BFP620 Transistor.”²

The new transistor is an excellent low-noise device and offers noise figure performance comparable to far more expensive GaAs metal semiconductor field effect transistor (MESFET) and GaAs pseudomorphic high electron mobility transistor (PHEMT) devices.

As one would expect with RF transistors housed in standard, low-cost surface-mount packaging, the gain of the BFP640 transistor chip is limited by the package parasitics as one moves above the 3 GHz range. Near 5 GHz, the bias current for minimum noise figure is about 5 mA.

A tradeoff of gain, noise figure and linearity resulted in the DC operating point of 3 volts V_CE and 8 mA collector current being selected. Table 3 gives noise parameters for the transistor at the 3 volt, 8 mA bias point. Note the excellent minimum noise figure values (F_MIN) and the modest, easy-to-handle optimum reflection coefficient magnitudes (Γ_OPT).

In designing the LNA for both low parts count and best possible noise figure, it was decided to avoid any external input impedance matching elements, if at all possible. In addition to the possibility of pulling the input impedance presented to the transistor further away from it's optimum impedance for noise figure, any practical matching element will introduce loss of some sort at the LNA input and, therefore, degrade the amplifier noise figure. This is especially true up at 5 GHz. A plot of noise figure versus frequency for the two-stage cascade LNA is given in Figure 5.

Refer to the schematic diagram in Figure 6 on page 18.

Lumped-element matching techniques are used exclusively, to reduce required PC board area. The output impedance matching circuit consists of L2 and L3 for the first stage, and L5 plus L6 for the second stage.

Due to the nonzero reverse transmission coefficient of the transistor (S12 ≠ 0), the output match favorably influences the input impedance match, with better than 10 dB input and output return loss values achieved across the band.

As a result, no input impedance matching elements are required — only an input DC block and a “choke” (L1 on first stage) to bring in base bias current is needed at the input. The value of L1 and L4 were chosen such that the chip coils operate just below their self-resonant frequency (SRF), ensuring that these elements have minimal loading effects on the input of each stage. A bill of material (BOM) is presented in Figure 7. Note that low-cost, industry-standard 0402 case-size chip components are used throughout.

As stated previously, the PC board used in this applications note was simulated within and generated from the Genesys software package. After simulations, CAD files required for PCB fabrication, including Gerber 274X and Drill files, were created within and output from Genesys. Photos of the PC board are provided in Figure 8, Figure 9 and Figure 10. A cross-sectional diagram of the PCB is in Figure 11.

The PC board material used is standard low-cost FR4. Note that each stage of the LNA may be tested individually; capacitor C2 (see schematic) may be positioned to steer the RF from the output of the first stage to the SMA connector on the bottom of the PCB, or, C2 may be used to link the track from this same RF connector to the input of the second stage, to permit testing of Stage 2 individually. The total PCB area consumed for a single stage is approximately 0.300 inch × 0.200 inch (7.6 mm × 5.1 mm), or approximately 40 mm², giving about 80 mm² for the complete two-stage amplifier. The total component count, including all passives, and the two BFP640 transistors, is 25.

Silicon-Germanium process enhancements are ongoing. Existing B7HF SiGe processes are being further modified to reduce contact resistances and improve transit times - resulting in even lower noise figure transistors. The first Infineon product to be released in this new B7HFe process technology will be the forthcoming BFP740. Figure 12 includes a noise figure plot of an early BFP740 engineering sample in a single-stage 5 GHz LNA application. The BFP740 shows an improvement of 0.2 dB to 0.3 dB in noise figure over the existing BFP640 in the same exact FR4/glass-epoxy PC board shown in this article, with better than 10 dB input and output return loss over the full 5 to 6 GHz frequency range. This represents about a 20 percent reduction in noise figure as compared to today's mass-production BFP640 transistor.

The BFP640 silicon-germanium RF transistor offers a high performance, power-efficient solution for a broad range of high-frequency low-noise amplifier (LNA) designs. The flexibility of this discrete RF device allows one part to fulfill several different functions. For example, the BFP640 may be used as an LNA or a PA driver amplifier in 5 GHz WLAN applications.

This article describes a high-performance, low cost, two-stage lumped-element discrete LNA design for the 5 GHz to 6 GHz frequency range. The high gain and low noise figure of the LNA presented enhances receiver sensitivity in WLAN and other 5 GHz to 6 GHz systems. Future enhancements to SiGe process technology will reduce noise figure values even further and result in devices with even higher performance potential than those in mass-production today.

1. “Understanding and Improving Network Analyzer Dynamic Range,” Application Note 1363-1, Agilent Technologies Inc. This applications note explains how to minimize the noise floor and maximize the dynamic range of a network analyzer.

2. “A High IIP3 Low Noise Amplifier for 1900 MHz Applications Using the SiGe BFP620 Transistor,” Applications Note AN060, Silicon Discretes Group, Infineon Technologies North America Corp. The section entitled “Effect of adding additional charge-storage across the base-emitter junction” explains the capacitor trick used to enhance third-order intercept performance.

Gerard Wevers is a wireless applications engineer in silicon discretes for Infineon Technologies North America Corp. (www.infineon.com). He received his B.S.E.E. degree from the University of California, Davis, and his M.S.E.E. from Santa Clara University. Jerry can be reached at gerard.wevers@infineon.com.

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