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This article is a discussion of a research project regarding the design and implementation of a Universal Mobile Telecommunications System (UMTS) base station transceiver.

The UMTS is a part of the International Telecommunications Union's (ITU) IMT-2000 vision of a global family of third-generation (3G) mobile communications systems. UMTS's vision includes enabling the next generation of a wireless information society. Goals include delivering high-value broadband information, commerce, and entertainment services to mobile users via fixed wireless, mobile wireless and satellite networks. UMTS offers data rates up to 2 Mbps with global roaming and other advanced capabilities⁸.

The idea of this project was to implement a tower-top transceiver system, which enhances the performance of the future UMTS wireless links. The usual disadvantage of not using tower top transceivers is the loss inserted between the Tx/Rx antenna and the base station processing unit. To overcome this obstacle, operators usually use expensive, low-loss RF cables with high-power capability. Nevertheless, since the typical cable length that connects the antennas to the base station's processing unit is in the range of 30 meters to 100 meters, the losses are still quite significant.

A novel (although not new) concept is to down/up convert the RF signals at the antenna site rather than at the base station, to overcome the before mentioned impediments. If this can be accomplished, then the system can use low-cost cables for the antenna-to-base station leg. The shift of the transceiver from the base station processing unit to the antenna site also improves the link budget, and, consequently, the coverage area of the wireless cell. This issue directly affects the cost of the wireless infrastructure.

The block diagram of the RF part of the transceiver is shown in figure 1. It comprises two waveguide filters², Tx and Rx, connected together and to the antenna via a duplexer, a power amplifier^1,3,6,7 at the transmitting side. At the receiver end, the it connects to a low noise amplifier (LNA). The flow of the signal at both sides (transmitting and receiving) is controlled by switches whose functionality will be analyzed later on this article (see figure 1).

The transceiver was designed to operate in the frequency-division duplexing (FDD) mode of the UMTS terrestrial radio access network (UTRAN). The design of the power amplifier has been simulated at a circuit level using optimization techniques with the a well-known circuit simulator and major manufacturer's software, and run on a standard computer. The measurements were carried out in the Microwave and Fiber Optics Laboratory (MFOL) in the Department of Electrical and Computer Engineering of the National Technical University of Athens, Greece.

The Tx and Rx filters are Chebyshev-type bandpass waveguide structures of fifth and fourth order, respectively^2,5. Waveguide technology was chosen because waveguides have very high-quality factor Q (compared to microstrip), and, therefore, exhibit benefits, such as lower insertion loss and very sharp cut off at out of band frequencies, while at the same time exhibiting excellent handling capability of high power signals².

The PA was designed in a class A type mode with an output power of 20 W. It is a two-stage design that has a linear gain of 25 dB and a voltage standing wave ration (VSWR) in both ports less than 3.5. The level of the second and third harmonics is less than -30 dBc.

The low noise amplifier exhibits excellent performance, having noise figure less than 1.3 dB within the bandwidth of 1.9 GHz to 2.0 GHz. It has a gain of 15.5 dB and the VSWR in both ports is less than 1.45:1.

Since the downlink performance in mobile communications depends primarily on the performance of the PA, its design is the most crucial. A well-designed PA is characterized by high-gain, high-linearity and stability, and high-efficiency compared to linearity. What makes this critical is that, traditionally, there is always a trade off among these various parameters in any given design as well as addressing good matching at the input and output^{4, 5}.

For this reason, special attention was paid, during the research, in selecting the proper transistors with respect to the lowest possible cost, the optimum large signal performance and without sacrificing the reliability of the whole system.

In table 1, a summarized set of the specifications addressing the PA is given. The values of the parameters are in accordance with the 3GPP/UMTS/FDD mode specifications.

To meet these specifications, a two-stage design for the PA was chosen. It is comprised of two Goldmos FETs from a major supplier.

The PA is a two-stage microstrip design with two external positive power supplies that feed the drain and the gate of the FETs, respectively (see figure 2 for the schematic of the PA). The occupied area is approximately 19 cm × 17 cm, including the bias circuits.

The matching procedure was based on Z-files, corresponding to input and output impedance of the transistors, given at the compression point of each FET. The input (output) circuit of each FET were considered as a one-port circuit that had to be matched to 50Ω termination. In this manner, four different circuits obtaining |S¹¹| <-10 dB in the desired bandwidth were separately matched, providing good performance for the whole amplifier. In figures 3 and 4 the simulation results of the S-parameters for each of the above mentioned FETs are illustrated.

To prevent current overdrive into the PA, the necessary fuses were placed before the drain bias circuit of each FET. Note that for the drain thicker lines (greater than 1 mm) were used due to the high level of current flowing through the drain bias circuits to the drain of the transistors.

The overall DC power consumption is approximately 150 W. Taking into account that the output power is approximately 20 W, the power added efficiency of the amplifier is about 13 percent.

The final layout of the PA is shown in figure 5. It is developed on a microstrip substrate R04003 whose characteristics are:

Relative dielectric permittivity:
ε_r = 3.38.
Height: h = 0.51 mm
Tand δ = 0.0035

The board was placed on top of a metal brick to achieve good thermal conductivity for the FETs and the regulators. For the same thermal reason, two fans were place below the metal brick in a “push-pull” arrangement.

The PA supplied power is +28 VDC. The measured results are shown in figures 6 and 7. These results were obtained by adjusting the bias current of the FETs according to the desired bias point and applying a +5 dBm signal at PA input.

The first set of measurements show that the maximum gain was 22.4 dB at 2.05 GHz, but that the input matching was not satisfactory at that frequency (-5 dB minimum value). However, the PA has been designed to operate at a compression point. This means that the input signal had to be at least +17.5 dBm. To achieve this, a preamplifier was decided upon that provided +17 dBm RF signal at its output. The preamplifier was tuned with small stubs and it's output applied to the PA. The final performance of the PA is illustrated in figures 8 and 9.

The bypass circuits are designed to bypass RF signals in case of an amplifier malfunction (PA or LNA failure) so the transceiver remains in continuous operation. For this feature, two RF switched circuits were designed (one for each PA and LNA). In particular, the PA's RF switching circuit was implemented on the board along with the other circuits (RF chain, biasing circuits, DC supply circuits, etc.). This section discusses, in detail, the functionality, implementation and performance of the above-mentioned circuits.

The complete block diagram of the PA, including the RF switches is illustrated in figure 11.

The block diagram consists of a low power switch (S₁), a high power RF switch (S₂) and a control circuit that controls both switches, simultaneously. When both FETs are in the “ON” state (high DC consumption), both switches are in position (1). If one of the FETs is in the “OFF” state, DC consumption is reduced to some µA, as listed in the particular devices' data sheets. When this occurs, the control circuit sets both switches in position (2), which changes the RF signal flow to bypass the PA.

Each switch is controlled by two DC logic voltages (0 VDC or +5 VDC). These logic voltages are provided by the control circuit at outputs (A) and (B) simultaneously (see figure 12).

The switch control circuit is comprised of several components and sub-networks such as comparators, diodes and logic “AND” sub circuits. To estimate the current that flows to the drain of the transistors two dummy resistances (0.1Ω) were added, in series, with the drain bias circuits and connected, in parallel, with two opamps configured as open loop.

The choice of the switches was based mainly on characteristics such as low insertion loss, high isolation in between the ports, and maximum input 1 dB compression point. According to the switches data sheets, one switch had an insertion loss of 0.4 dB while the other had an insertion loss of 0.2 dB. The simulation results expected a drop of 0.7 dB for the PA gain at normal operation and a 0.85 dB insertion loss in the “OFF” state (without considering the board's SMA connectors' insertion losses).

The experimental losses were higher than the typical losses (the summation of switches insertion loss in each case — “ON” and “OFF” state) because of the effect of steep discontinuities (steep changes at the width of the microstrip around the input switch).

A complete low cost tower top PA has been developed, designed and constructed. The design includes a self-bypass option in that allows continuous operation in case the PA malfunctions. The design meets the UMTS specifications and measurements, therefore is can be implemented as a part of a UTRAN base station transceiver operating in FDD mode.

1. P.L.D. Abrie, Design of RF and Microwave Amplifiers and Oscillators, (Artech House 1999).

2. G. Mattaei, L. Young, E.M.T. Jones, Microwave Filters, Impedance Matching Networks and Coupling Structures. (Artech House Books 1980).

3. Sedra and Smith, Microelectronic Circuits (1994).

4. N. Ouzounoglou, D. Kaklamani, Telecommunication Electronics (NTUA 1999).

5. N. Ouzounoglou, Introduction to the Microwaves (1994).

6. Nick Pothecary, Feed forward Linear Power Amplifiers (Artech House).

7. Perry Edwards, Microstrip Design (1995).

8. UMTS Forum, Report 1, 1997.

Yorgos Mitropoulos received a diploma in electrical engineering and computer sciences from the National Technical University of Athens (NTUA), Greece, in 2001. He is currently working towards his Ph.D. degree. He is also working for the European project MELODY. He has contributed to European and national projects. His research interests include microwave and millimeter wave telecommunication systems on isotropic and anisotropic substrates, MIC and MMIC design and adaptive antennas. He may be reached via e-mail at gmitr@esd.ece.ntua.gr.

Dr. Yorgos Stratakos is Senior Researcher at the Institute of Communications & Computer Systems, Microwave & Fiber Optics Laboratory. His research interests include microwave and millimeter wave telecommunication systems, radar, microwave CAD linear and nonlinear techniques, MIC and MMIC design, conformal array systems, adaptive antennas and automated microwave measurement techniques, and advanced packaging techniques. He has contributed as a key re-searcher to projects RACE, ACTS, COST, ESPRIT and national programs. He may be reached via e-mail at george@esd.ece.ntua.gr.

Ilias Tsopelas received the diploma in electrical engineering and computer sciences from the National Technical University of Athens (NTUA), Greece, in 2001. He is currently working towards the Ph.D. degree. He also works for the Protean Technologies Co. (Athens) on software development for e-commerce applications. His research interests are in microwave telecommunication systems, optical fiber communication networks, and photonic crystal fibers. He may be reached via e-mail at itsop@central.ntua.gr.

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