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RF engineers designing complex converter and frequency synthesizer subsystems must analyze each noise and spurious contributor separately to gain confidence in proposed designs. The goal of this article is to systematically address some of the subtle effects that engineers spend so much time chasing. The focus will be on signal generator systems, since those systems usually limit the BER, jitter, or pulsed phase noise performance in communications and radar systems. In addition, I hope to offer a few useful spreadsheet tools (inherited from my accountant friends), to help predict some of the effects discussed. Packaging is beyond the scope of the article.

It may seem intuitively obvious to define requirements and goals before a project begins, but it almost never happens that cleanly. Often, system requirements are changing while the RF designs are proceeding.

Rather than waiting until every thing is defined neatly, engineers are often required to forge ahead in the dawn of a project. What I promote is simple; Do your homework — and the homework of others — early until you have a set of requirements that are clear enough for you to begin work. Spend some time with the systems engineers or customers and get a sense of the range of uncertainty in the critical requirements area. Do some analysis on your own to try to define what you expect is achievable versus what might be required by an application. Develop a cost model and develop a clear picture in your mind about the performance cost drivers. Methodically define each input to your signal generator subsystem and each output.

The requirements that I want to look closely at in this article are the phase noise contributors and spurious, along with the defined noise on the DC supply including its ripple characteristics.

In new frequency subsystems, the critical characteristics to model include:

• realizability of the frequency plan;
• mixing product modeling;
• PLL phase noise;
• settling time modeling;
• multiplier chain phase noise modeling; and
• DC power supply noise modeling.

Architecture origination is a complex subject that exceeds the scope of the article. My goal here is to develop the tools to evaluate any given solution. In brief, architecture origination includes:

• trading several general solutions for the primary noise and switching speed requirements;
• blocking out the architecture;
• trading multiple technologies for each block; and
• confirming realizability.

The realizability of a frequency plan solution must be validated for performance margin, parts availability, manufacturability and cost metrics.

Precision signal generators normally have a frequency plan that includes frequency conversion by mixing and multiplication. Modeling of mixing products can be done using various tools, but all are subject to validation of the selected mixer characteristics, at the specific operating levels. It is useful to start your analysis with a known mixer model, with product levels defined for the N × RF ± M × LO through at least 7^th or 8^th order products. An excellent soft tool for this is Spurlot: Mixer Spurious-Response Analysis With Tunable Filtering - Software and User's Manual by Robert Kyle (New York: Artech House, 1997), which allows double conversions and user-defined mixer tables. Also, Spurlot has a nice filter definition function built in to help develop individual specifications for filters.

As the design solidifies, it is better to get measured mixer data for use in the application. Below is an example of the typical output available.

In either a down conversion or an up conversion, the mixer should be treated as a phase noise summation node of the two input ports of the mixer being used. It should also be given a residual noise contribution equivalent to its effective noise figure (conversion loss) and flicker noise (1/f noise) contribution.

These effects can be ignored when the signal levels are high at both ports of the mixer, but make sure that it genuinely is not important. Sometimes in an effort to reduce a certain spurious product, the drive levels to a mixer can be adjusted to remove the spurious problem, but this can cause problems when the conversion S/N levels get within 10 dB to 15 dB of the noise floor of the conversion stage. It is straight-forward to determine additive equivalent net noise from two sources

(PN_total = PN_A + PN_B) (1)

This must be done in absolute power units, such as watts or milliwatts, to add the powers, then reconverted to dBm as follows;

[PN_{total dBc} = P_{carrier dBm} - PN_{total dBm}, PN_{total dBm} = 10^×Log (10^{((PNA dBm)}/10) + 10^{((PNB dBm)/10))}] (2)

The general expression for the additive contribution of noise source A, X dB below noise source B can be derived from a simple sum of powers. The resulting expression is as follows:

where X is the noise difference between two sources in dB.

This is a helpful chart to paste on the wall in the lab near the phase noise test gear to account for test source noise contribution.

Modeling of PLL subcircuits has been exhaustively covered by numerous authors because of its importance as an RF building block. I will treat it as a block in our discussion for simplicity. The circuit design techniques involved cross several technical fields including digital sampling, analog operational amplifiers, control systems and oscillator design/characterization. The PLL simulator tool provided by Randy Rhea is cost effective and accurately includes most key noise contributors such as resistor noise, integrator noise, VCO noise, reference noise, divider, and PD noise. An example of a simple 2000 MHz PLL is shown below with 10 kHz closed loop bandwidth. Phase noise verses offset data from a PLL simulation can be extracted and used as a block in the overall signal generator noise analysis, as will be shown later.

Frequency multipliers are fundamental building blocks of most microwave high performance systems. As components, they come in the form of step recovery diode (SRD) multipliers, Schottkey diode varistor multipliers, bipolar junction transistor (BJT) multipliers, field effect transistor (FET) multipliers, Yttrium iron garnet (YIG) multipliers, and varactor multipliers.

All multipliers use the nonlinear characteristics of the particular technology selected to create harmonically rich spectrum. The desired products can be selected from the spectrum and undesired products must be rejected.

A common physical property of all multipliers, regardless of technology, is the characteristic translation of delta phase changes from the input to output. The translation of phase is linear with multiplication factor (dfout = N*dfin).

Multipliers are not capable of warping time, so doubling or tripling the phase change per unit time translates to doubling or tripling the frequency since frequency is just the term Iuse for rate of phase change.

This seems intuitive but the consequences of this simple fact are too often ignored in the design phase, except for the desired effect of frequency multiplication. The undesired effects come in the form of ignored modulation terms and spurious translation.

It is a given that phase noise can be described as a statistically determined spectral phase modulation mask superimposed on an ideal carrier. The instantaneous phase fluctuations are multiplied by N which in the noise power domain is a 20*Log (N) function. This means that the input noise of a multiplier block is translated to the output by summing all noise sources present at the effective input, then increasing this noise power by 20*Log (N). The noise sources to consider for summation before adding the 20*Log (N) factor include input phase noise, kTB + NF Noise, and device 1/f noise from amplifier or multiplier stages. The summation must be done with all terms converted to a common unit of absolute power. The simplified signal flow diagram shown below is the basis for the Excel spreadsheet tool available by request from Trak Microwave Corp (www.trak.com).

The screen capture of the cascaded phase noise tool shown in figure 7 provides total cascaded phase noise and integrated noise for complex chains. It includes the ability to analyze the cascade of amplifiers, multipliers, filters and passive losses.

Noise associated with the flicker noise (1/f noise) in semiconductor devices is important primarily in oscillator design and early stage multiplier chain devices. Schottkey diode based doublers are the lowest flicker noise devices with typical 1/f corners under 1 kHz, while BJT devices tend to range between 5 kHz and 15 kHz for RF/microwave transistors compared to metal semiconductor field effect transistor (MESFET) devices with 1/f corner greater than 1 MHz.

Recent joint work with Dr. Larry Dunleavy and Clemente Toro, Jr., from the University of South Florida, has shown that new silicon germanium (SiGe) devices with Ft>30 GHz are capable of 1/f corners an order of magnitude better than classic MESFET devices. It is interesting to note that the SiGe 1/f noise corners vary with bias voltage, so detailed characterization is very important in critical applications. Figure 8 shows a plot of 1/f verses bias current for a new SiGe device demonstrating bias dependency.

Similarly, multipliers take the instantaneous phase deviation associated with spurious products injected at the input or interstage from bias ripple, and then multiply the deviation by N to the output. This means that a signal source, such as a crystal oscillator at 80 MHz, feeding the input to a X128 multiplier to X-band would need to have phase modulation and frequency modulation (PM/FM) spurious products lower than -102 dBc to achieve an X-band spectrum that has all spurious less than -60 dBc (given 20*Log(128) = 42 dB). This is caused by the direct multiplication by N of the angular deviation of peak phase deviation.

Another subtle effect of a similar nature occurs when amplifiers or active multiplier stages are modulated by DC bias ripple or noise, which I will address in the next section.

DC power supplies can severely hurt the performance of precision RF sources if not managed carefully. It is critical to understand both ripple and noise to design adequate attenuation to prevent modulating the RF sub-blocks within the system. First, I will review some foundational concepts of noise voltage, and then Iwill be able to address the coupling of noise voltage to phase noise and spurious effects.

All electronic devices produce a noise power. The one I am most familiar with is the noise power (Nt) at room temperature,

where k is the Boltzmann's constant (1.38×10^-23 J/K), T is the temperature (typically room temperature or 17C + 273C = 290k) and b is noise bandwidth for normalization (Hz).

To convert from W to mW and dBm, I can use the following examples.

Nt = 4 × 10^-21 W in 1 Hz BW (5)

Converting to mW

Nt = (4 × 10^-21 W) × (1000 mW/W) = 4 × 10^-18 mW in 1 Hz BW (6)

Converting to dBm

Nt = 10*Log (4×10^-18 mW) = -174 dBm/Hz (7)

This is the basis for cascaded noise calculations in receivers and local oscillator multiplication chains. The noise figure of a device is simply the characteristic effective input noise power ratio, relative to -174 dBm/Hz.

This is a good number to commit to memory since it can be easily scaled to other measurement bandwidths. Many analysis tools in use today handle cascaded receiver noise very well. The subject is brought up here just to remind us of the basic physics built into the universe we work in and to provide some background to cascaded multiplier network discussion and other phase noise contributors. It is often helpful to convert thermal noise within a resistor into a noise voltage for circuit and system analysis.

The simplified expression for resistor noise voltage is

where Vt is the rms noise voltage and R is the selected resistance in ohms. The remaining terms are defined in previous equation.

For examples, calculated for a 1000 ohm resistor

V_t = SQRT (4*1.38 ^× 10^-23*290*1000*1) = 4nV√(Hz (9)

This result is useful to memorize also, since the value can scaled by the square root of the resistance ratio and to other bandwidths. When using resistors in bias networks or RC filter networks, it is important to keep this in mind because large value resistors are noise generators.

Operational amplifier input noise is usually specified in these terms. For example, the classic OP-27 low noise amplifier is specified to have about 3.5nV/√Hz, which can be translated by circuit gain. Voltage regulator circuits are usually specified in terms of total noise (~10uVrms) within their bandwidth so to estimate the equivalent noise in a 1 Hz BW simply divide by square root of the regulator output bandwidth.

Vreg noise = 10uVrms//√(10 kHz) = 100nV√(Hz (10)

It is not uncommon to find families of regulators that have 200 nV/√Hz to 300 nV/√Hz due to the scaling nature of linear regulator designs from an internal noise reference voltage. Noise voltage in systems must be managed tightly to achieve difficult phase noise requirements normally expected in modern systems. Active or passive RC filters can be used to attenuate noise to meet the system requirements.

To use the voltage noise concepts I need a transfer function from noise voltage to AM/FM/PM noise. This article will focus on the dominate mechanisms so I will ignore AM contributions since they are almost always less significant and get converted to FM/PM noise through imperfect nonlinear limiting devices. Frequency and phase modulated signals can be expressed by a Bessel function, and for small angle modulation β<<1 the linear approximation can be shown to be reasonably accurate for spurious and noise power products less than -30 dBc. Shown below is the linear approximation to the Bessel functions for FM and PM.

For FM modulation the spurious may be calculated by

where Fm is the modulation rate or ripple and dF is peak frequency deviation. Similarly, for phase modulation it is

where dф = peak phase deviation.

We typically use FM spurious calculations for oscillator blocks that have frequency/volt deviation sensitivities, such as VCO or crystal oscillator pushing and tuning sensitivities.

Example 1: Crystal oscillator at 80 MHz with a tuning sensitivity of 10 ppm/volt and pushing of 1 ppm/volt. Given a switching DC power supply with 100 mV pk ripple at 100 kHz rate used as the tune voltage. Find SSB spurious.

Use FM equation: SSB= 20*Log((100e-3*10e-6*80e6)/(2*100e3)) = -68 dBc

Example 2: Amplifier made from MESFET microwave transistor has a sensitivity of 10 deg/volt of bias change. Given the same DC converter described in example 1. Find the SSB spurious.

Use PM equation: SSB=20*log((100e-3*10*π/180)/2) = -41 dBc

Phase noise can be similarly calculated from noise voltage generated by DC power supplies when coupled to oscillator circuits by using the FM equation above modified to convert the rms noise voltage to peak voltage. The phase noise in oscillators from noise voltage may be calculated by

where Kv is the tuning sensitivity in Hz/volt, Vn is the noise voltage in nV/√Hz and Fm is the frequency offset.

Example 3: VCO at 800 MHz with a pushing sensitivity of 100 kHz/volt. Given a switching DC power supply, with 126.5 nV/√Hz noise at 25 kHz offset used as the tune voltage. Find phase noise 25 kHz from the carrier due to power supply noise.

Use Phase Noise equation:

SSB dBc/Hz = 20*Log((100e3*√2*126.5*1e-9)/(2*25e3)) = -128 dBc/Hz

A PLL functions as both a multiplier and a tracking filter relative to the reference input. This means all noise and spurious riding on the reference will be multiplied by the effective N (Neff = Nvco/Nref) of the PLL to its output within the control band width and attenuate reference related spurious and noise outside the loop BW by approximately 20 dB/deacade. This can be used to your advantage if you are supplied a reference source that is too noisy or has spurious far from the carrier.

If the noise is injected into the VCO or post amplifiers within the control loop there is some significant attenuation possible. The loop will not attenuate their effects beyond the control BW, but will attenuate the spurious or noise on the VCO increasing -40 dB/decade within ½ loop BW as you go towards the carrier. This is why a PLL improves the phase noise of a VCO within the BW. This same effect works to attenuate spurious, noise and vibration induced problems superimposed on the VCO. The approximations to the attenuation are easy to implement within a spreadsheet, although a more rigorous solution would be to use the calculated loop transfer function.

This can be very complex, so I will limit this discussion to setting up a model for a basic system. An Excel spreadsheet is an excellent way to use the formulas and solutions offered to quickly build a spurious and noise model for a custom application. Start with a high-level block diagram and an input phase noise/DC noise specification.

From there you can use the concepts discussed to build a total noise model for the converter system local oscillator. As simple model as shown below will help organize your spreadsheet math model.

The goal of this article was to provide a methodical way of managing noise and spurious in complex source based subsystems such as converters.

The checklist suggested provides a good tool, if used for design review purposes. It is always helpful at the beginning of the design to make sure a clear connection between the expected performance of the microwave assembly and the supplied coherent reference source and the available DC power supplies. Additional tools were offered to calculate cascaded phase noise, and formula were suggested to predict power supply noise and spurious effects.

The complex subject of package isolation is very important in control of cross talk and spurious coupling within tightly integrated assemblies. Package isolation is a subject that has become more critical and risky as cell-phone handsets shrink and military equipment is designed into SEM-E or VME Euro cards.

I is hope the compilation of commonly known principles offered here will help microwave subassembly designers get it done right, and get it done sooner. Then we can all spend more time with our families and less time chasing birdies late at night behind schedule.

William F. Graves is the chief technology officer of Trak Microwave Corp. (www.trak.com). He graduated from the University of South Florida with a BSEE degree in 1985, and has been involved in the design and management of RF/microwave low phase noise subassemblies for radar systems and microwave Satcom for 18 years. Graves can be reached at wgraves@trak.com.

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