The fusion of Command, Control, Communications, Computer, Intelligence, Surveillance, and Reconnaissance (C4ISR) requires flexible and adaptable cutting edge RF and digital processing hardware. Such hardware must support features such as scalability and reconfigurability that are necessary to support the intelligence collection missions. Additionally, it must handle the wide range of waveform requirements of these future systems.

The best option for technology that forms the backbone of these systems is based on software-defined radio (SDR). SDR systems designed for C4ISR require high performance digital processing resources capable of very high bandwidth, low latency, deterministic data and control paths that are tightly integrated with the RF to support waveform flexibility.

Programs such as joint tactical radio systems (JTRS), aerial common sensor (ACS) and warfighter information network-tactical (WIN-T) require the ability to reconfigure and run multiple channels of a wide variety of waveforms with variable bandwidths and processing requirements over a wide RF frequency range.

ACS and WIN-T have the mandate to improve signal quality and provide direction-finding capability to these systems using digital beamforming. Beamforming presents certain challenges in the RF and digital domain above the single channel radio requirements to maintain a coherent observation environment across a spatial plane. This article will address the SDR design considerations when building a C4ISR system supporting beamforming on a diverse set of waveforms. Many of the concerns addressed in this paper are directly applicable to the transmit path, however; to narrow the scope of the discussion, only the receive path will be examined.

Beamforming is a signal processing technique that uses spatial filtering to enhance communication system directivity. Multiple independent electro-magnetic waves propagating from different directions towards the sensor array can be resolved using statistical processing, even if their frequency spectrums overlap. There has been significant research in the area of beamforming algorithms and current applications range from cellular base stations to military surveillance.

A similar application that uses multiple spatially-distributed sensors to estimate signal angles-of-arrival is direction finding (DF). For both applications, it is generally assumed that the analog data is captured coherently across all of the sensors.

In beamforming and DF applications, direction of arrival and steering angle computations are based upon the relative phase and amplitude between sensors. An electro-magnetic wave front incident upon the sensor array, illustrated in figure 1, will result in an incremental phase shift between sensors, depending upon the angle of arrival. To accurately estimate the original direction of arrival at the array, the phase/amplitude relationship must be preserved through the RF conversion and digital processing chains. Any degradation to the signal quality will limit the ability of the processor to compute directions of arrival, or perform interference cancellation.

A system that preserves this phase information throughout the conversion/digitization chain and from channel-to-channel is considered “phase coherent.”

Phase coherence in RF hardware is most often accomplished by either (a) sharing local oscillators between channels, or (b) using direct synthesis of local oscillators. This applies where local oscillator (LO) signals are directly related to a common reference source (through heterodyning, multiplication, etc.), and have negligible non-phase coherent phase contributions.

The primary limitations of phase coherent performance in the RF tuner are:

• Channel-independent, time-varying amplitude and phase modulation of the local oscillator;
• Time-invariant, uncorrected interchannel phase and amplitude error; and
• Short-term, interchannel phase and amplitude drift versus temperature.

Any local oscillator will exhibit random amplitude and phase modulation components, which can be characterized mathematically as:

Where θ_n(t) and e_n(t) are random variables, and ø is a constant

Generally, the amplitude modulation component, e_n, will have a minimal contribution to the overall noise due to limiting in the LO amplifier and mixer. Additionally, the phase offset ø will remain constant and can easily be calibrated out. Therefore, random phase modulation is the primary concern when analyzing phase coherent system noise performance. Any phase noise modulation on the LO will be impressed upon the input signals during the mixer conversion. This additive phase noise modulation will ultimately limit the signal-to-noise (S/N) ratio required for frequency/phase (FM/PM) demodulation.

Uncorrelated phase error between channels will similarly degrade beamforming, or DF accuracy, in a multi-channel phase coherent system application. This phenomenon applies to any LO in the super-heterodyne conversion chain, as well as analog/digital (A/D) sample clocks.

Shared or synchronous local oscillators will result in correlated phase noise that is consistent across all channels and does not introduce any additional error in most applications. Note that coherence between channels must be maintained throughout the digital receiver to take advantage of coherent processing.

Generally, the wideband or tunable LOs represent the most significant contributors to the overall phase noise due to higher frequencies, wider frequency coverage, and large ÷N ratios. Narrowband fixed or low frequency local oscillators may have sufficiently low phase noise to disregard their overall noise contributions. Figures 2 and 3 show examples of single sideband phase noise plots of a typical wideband UHF local oscillator and a narrowband, lower-frequency local oscillator, respectively.

To estimate the impact of phase noise on signal-to-noise ratio in the demodulator, the phase noise spectral density is typically integrated over the bandwidth of interest. Integrated phase noise (or incidental phase modulation) can be calculated based upon the following equation:

Where S(f) = single-sideband phase noise spectral density, integrated phase noise modulation (wideband LO example) ∵ 0.9° RMS and integrated phase noise modulation (narrowband LO example) ∵ 0.09° RMS.

Based on this analysis, it may be acceptable to distribute the tuned oscillator only. This would simplify the LO distribution with minimal degradation to S/N performance. However, there are disadvantages to system architectures that use a combination of distributed local oscillators and independent fixed local oscillators. Independent local oscillators generated using indirect synthesis techniques may result in non-deterministic phase offsets between channels.

For example, a voltage-controlled oscillator (VCO) that is phase locked to a reference signal can assume multiple unique phase states with respect to the reference, when R and N counters are not equal to one. Since the relative phase error is constant, this can typically be calibrated out in the digital signal-processing domain.

Typically, the LOs, which represent the most significant phase noise contributors, are distributed among channels using an LO distribution system. The master channel then provides local oscillator signals for all slave channels.

Some design considerations regarding LO distribution systems are:

• Signal-to-noise ratio of local oscillator signals;
• Isolation between independent local oscillators;
• Short-term amplitude and phase drift over temperature; and
• System configuration flexibility.

When critical LO signals are distributed across multiple channels, there is ample opportunity to degrade the S/N ratio of the carrier. Depending upon the sensitivity of the receiver, this may result in degraded performance in some slave channels. Generally, significant mechanical effort goes into avoiding LO crosstalk within the tuner module. Similar effort should be made when designing an LO distribution module to prevent degradation in spurious performance.

Coss talk due to cables and within printed circuit (PC) boards can result in mixer spurious and time-varying phase drift can be introduced by routing LO signals over coaxial cables and peripheral LO distribution modules. These components can be characterized to estimate their overall contribution to the phase error budget. Depending upon the application, the system configuration may need to be changed on the fly. The need for multiple master channels, and the ability to switch between master and slave modes without recabling can complicate LO distribution design.

Phase error due to local oscillator noise and phase-locked loop (PLL) ambiguities can be minimized using LO distribution techniques. However, phase and amplitude drift due to other tuner components should also be considered. RF tuners consisting of amplifiers, mixers, filters, and attenuators will exhibit some amplitude and phase mismatch between channels as these components vary over time and temperature.

Generally, the phase sensitivity of a device is inversely proportional to its bandwidth. For example, a wideband RF amplifier should exhibit very little phase variation over the signal bandwidth of interest, whereas a narrowband IF filter may have significant phase variation.

Surface acoustic wave (SAW) filters are often used for IF filtering in wideband digital receivers, due to their small size, and excellent shape factors. Depending upon the construction material, wideband SAW filters may have significant phase delay, and large temperature coefficients. This can generally be predicted from datasheet parameters, as shown in the following example:

Center frequency: 70 MHz
3-dB bandwidth: 30 MHz
Time delay: τ_SAW ≅ 1.07 µs
Temperature stability: -94ppm/°C

Therefore:

When trying to minimize phase error through an RF channel, phase drift is obviously a significant contributor. Regulating the device temperature can be an effective means of minimizing phase variation.

An example of measured interchannel phase matching between two coherent tuner channels with temperature-regulated SAW filters is shown in figure 4. These plots show the interchannel phase error across a 25 MHz passband, at +20° C and +40° C. The interchannel phase drift versus temperature has been reduced to less than 0.25 deg/° C.

The most effective means of correcting interchannel phase and amplitude error in a coherent system is to measure phase and amplitude response of each channel using a common source, and calibrate this factor out in the digital signal processor (DSP). Depending upon the system architecture, this can be accomplished with a signal generator, which is phase synchronous with the receiver LO signals, distributing to all channels, and then tuning across the desired frequency spectrum. The relative phase of each channel with respect to a common reference can be measured in the DSP and stored to create an error-correction table.

Depending upon the instantaneous bandwidth and desired accuracy, this may require multiple points at each tuned frequency. The system must be recalibrated periodically to account for short-term interchannel variations resulting from temperature fluctuations, power supply variations, etc. To effectively correct for these interchannel phase and amplitude errors, calibration must be done at intervals that are much less than the short-term effects. Other calibration techniques include self-calibration on an arbitrary received signals, and compensation using analog phase shifters.

In C4ISR systems, the output of the RF front end is typically a wideband output that will be digitized, channelized and processed. To maintain the phase coherence of the RF front end through the SDR, the sample clocks of the analog-to-digital conveters (ADCs) must be phase coherent and the signal processing elements must maintain a time reference to provide a method of associating samples across the spatial plane.

A typical block diagram of single channel architecture for an SDR is illustrated in figure 5. The RF front end's wideband output is an IF sampled by a high speed ADC. The sample rate is chosen such that it captures the signal bandwidth while considering the potential aliasing of an IF greater than that of the required by Nyquist. The output of the ADC is attached to an field-programmable gate array (FPGA) responsible for such functions as channelization, equalization, filtering, and carrier tracking. The FPGA typically reduces the input bandwidth to a more manageable rate for a DSP. The DSP will demodulate the signal, or in other words, convert the signal from symbols to bits. The bits are then passed to a general-purpose processor that performs link processing. This is protocol or medium access control (MAC).

C4ISR systems consist of multiple channels that can be operated in three distinct modes. In the first mode, the channels are operated independently as in a JTRS multi-channel radio. In the second mode, the channels can provide cross band coordination for gateway functionality, as in a WIN-T system. In the third mode, the channels can be coordinated to provide spatial processing.

Ideally, the digitized IF, FPGAs and DSPs are all be connected by a high-speed, low latency, deterministic interconnect fabric such as RapidIO. RapidIO provides a packet switched connection that allows the waveform to establish a connection from any device to any other device. This is particularly useful for beamforming algorithms since the data across the spatial plane must be shared between multiple processing elements.

Oscillators for digital components typically have stability uncertainty in the 1 ppm to 10 ppm range. In beamforming the systems where multiple ADCs will be employed, there would be a significant discrepancy in clocking rates between them. To have an effective process, the ADCs must be in lock step so that their observation period is identical across the spatial plane. This would be accomplished by providing a timing reference clock feeding the ADCs. Equal length cables will be used to distribute the clock to eliminate clock skew.

The sample rate is calculated based on the bandwidth of the signal while considering the IF frequency offset. The IF frequency can impose an undersampling condition when the IF frequency, plus half of the bandwidth, exceeds the Nyquist frequency required to capture the bandwidth. In simplistic terms, the sample rate is chosen to both satisfy Nyquist and center the bandwidth at f_s/4. The minimum sample rate is typically selected to be a multiple of 2.5 as opposed to 2, to compensate for the filter rolloff. An example wideband output of an RF tuner is 25 MHz centered at 16.25 MHz. This yields a sampling frequency of 65 Msps (16.25 Msps • 4 = 65 Msps), which satisfies the minimum sample rate (2.5 • 25 Msps = 62.5 Msps).

Other practical terms for consideration are the oscillator's stability and Doppler effect.

Oscillator stability leads to center frequency uncertainty. The output bandwidth of the digital down converter (DDC) should be expanded to compensate for this uncertainty. Additionally, for moving sources of RF energy, the relative velocity between the source and the receiver induces a Doppler frequency shift. The output bandwidth of the DDC will need to take into account the worst-case scenarios for both phenomena, and compensate by expanding the captured bandwidth.

From the beamforming perspective the oscillator stability's bandwidth uncertainty contribution is common across the array, so it will require basebanding adjustment, but it will not impact the beamforming algorithm's effectiveness. Also, the relative difference in Doppler shift between sensor elements is negligible since the separation between elements is orders of magnitude less than the distance between the elements and the source. It will not provide any appreciable error in the beamforming calculation.

Referring to the SDR architecture, the input to the first processing stage (the FPGA) is the wide band output of the digitizer. This FPGA serves as the processing engine to enable the physical layer of the waveform. For example, in a frequency division multiplexed (FDM) channel structure, a DDC intellectual property (IP) core is implemented in the FPGA to select one channel.

The design of the DDC consists of a quadrature mixer with successive stages of filtering and decimation to extract the complex baseband samples representing the channel of interest. The mixer is designed as a pair of numerically controlled oscillators (NCO) with one in phase mode and one in quadrature mode. They are implemented with a lookup table of values representing the sinusoid. To select a frequency within the wide band input to downconvert, the bandwidth and center frequency of the desired signal is programmed into the DDC. The programmer also has the ability to reset the initial phase of the NCO.

To perform beamforming on an FDM channel, a set of DDCs across the spatial plane (one following each of the ADCs) is tuned to the same frequency and bandwidth. Before beamforming can be performed, the NCOs on each DDC must be initialized to the same initial condition. This can be achieved in two ways. First, by imposing synchronous clocking at all levels of the process. Second, by time tagging the data so that the data can be processed asynchronously (given that the time/spatial relationship of the data can be embedded in a channel packet). For some system configurations, the latter is the preferred method since it removes the deterministic requirements on the FPGA processing clock and NCO synchronicity.

For this method to work, a synchronized time tag across the spatial plane must be applied at the time of sampling. Data is packetized with a header containing event information, including the time tag. When an NCO initialization must be applied to the DDCs, it can be inserted into one packet corresponding to the same time across the DDC set. The packet may be processed at any time and still maintain the requisite time/spatial alignment.

A much more challenging circumstance is the coordination of frequency hopping waveforms. This requires that the RF and DDC sets are tuned and NCOs initialized synchronously. This can be handled with a control path to the RF and frequency lookup table or “TRANSEC” interface on each of the FPGAs. The FPGAs having a common timing reference derived from the common sample clock will enable the system to synchronously control the hop tuning. This will require strict DDC tuning/initialization determinism, not required in the time tagging method. Time tagging is still useful for data association in the beamforming algorithm in this method.

After the data is downconverted, the time aligned data packets from the DDC set will be routed to a processing resource for the beamforming algorithm to be applied. For interference mitigation, the algorithm will phase align the data, apply weights and sum. This improves the quality of the waveform by decreasing the fading effect and rejecting interference. For DF, the relative phase offsets are calculated to create an angle of arrival (AOA) determination.

Following the beamforming pro-cess, the modem functions will be performed in the signal processor and the bits will be shared with the general purpose processor (GPP). The only real-time concern at this level of processing involves the latency and synchronization of the return path for the communications aspect of the C4ISR radio. If the return path could also support beamforming, the feedback to the signal detection could either be in the form of space division multiple access or jamming and would require different levels of real-time performance.

This article highlights both the RF and digital concerns involved in designing a C4ISR beamforming system. The merging of the technologies provides some insight into the similarities between the analog and digital concepts and their performance limitations in terms of synchronization methods.

The reader can also see the inherent benefits of flexibility, scalability and reconfigurability of the SDR system that enables one multi-channel radio configuration to perform a wide variety of tasks, relying solely on the mission needs of a current tactical scenario.

Required flexibility of C4 requirements relate to the bandwidth that can be supported with respect to movement of data, voice and video. The choice of the components must be scaled to support the fastest data rate and most complex waveform structure. The system should also be designed to facilitate technology insertion to promote the support of the newer, higher bandwidth standards as they emerge.

Direction finding is just one ISR function, and to be comprehensive, it would require the systems architect to scale the signal processing hardware to accomplish other tasks not described in this article. However, the hardware described can accomplish a great deal. Given the flexibility of an SDR, the system described can be programmed to scan over a very wide bandwidth by operating the tuners independently. Once a signal of interest is identified, a mode change can be established and a beamforming calculation can be made.

The flexibility of SDR allows a multi-channel radio to morph into C4ISR missions with reconfigurable software defined modes.

Reese S. Bovard is the director, applications engineering and services at Spectrum Signal Processing. He is an M.S. Electrical & Computer Engineering graduate from Carnegie Mellon University and has over fourteen years of experience in real time embedded systems engineering and software design. His work experience includes software defined radio systems engineering, statistical analysis, signal processing, ATR filter design, image analysis, and system control software design. He can be reached at: reese_bovard@spectrumsignal.com.

Adam C. Bush is a RF design engineer at Signia-IDT Inc. (formerly Watkins-Johnson Co.) where he develops wireless communication and surveillance products. He received his Master of Science, and Bachelor degrees in electrical engineering from the Georgia Institute of Technology. He can be reached at adam.bush@signia-idt.com

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