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Recent enhancements in the proprietary multifunction self-aligned gate (MSAG) process has enabled M/A COM to develop a new line of gallium arsenide (GaAs) high-power monolithic microwave integrated circuit (MMIC) amplifiers that offer improvements in bandwidth, integration, power-handling capability, noise, and reliability. Covering L through X-bands, these MMICs are designed for electronic warfare (EW), radar and military and commercial communications applications. In essence, they offer power outputs ranging from 8 W to 20 W and bandwidths ranging from 30% to two octaves. The results obtained are summarized in Table 1. These parts have been qualified over temperature, drain voltage, input power and frequency. Figure 1 shows the die layout for two members of this new family.

The MSAG is a versatile process that provides excellent performance for power amplifiers, low-noise amplifiers (LNAs), limiters, and control functions up to 20 GHz. A proven advantage of the MSAG process is its robustness at the next level assembly. MSAG does not use air bridges, employs polyimide scratch protection, and has no hydrogen poisoning susceptibility. These features all lead to easier handling, higher assembly yields, and lower assembly costs.

In fact, it is a planar, ion-implanted MESFET process. The power amplifier device in this process is 5 A FET that provides 800 mW/mm of output power at 65% power-added efficiency (PAE) at 10 GHz and 10 V. As shown in Figure 2, the MSAG process has no gate recess step, thereby improving consistency. In this process, the active devices use 0.4 µm gates deposited via low-cost optical lithography, leading to higher throughput and lower cost. As a result, the process is highly repeatable and cost effective. In addition, its 5 A FET is highly reliable. Extensive accelerated life testing demonstrates a one million-hour MTTF at a junction or channel temperature of 170 °C. This result is shown in Figure 3, an Arrhenius plot.

A unique feature of the MSAG process is its intra-wafer, intra-reticle uniformity. This characteristic allows the efficient reactive combining of several tens of mm of FET gate periphery in a single stage. The primary limitation of FET periphery in the output stage is a trade between the loss (dissipative and mismatch) of the output matching network (OMN) and the operating bandwidth. The function of the OMN is as an impedance transformer between the idealized load line impedance of the output stage FETs and the system impedance, typically 50 Ω. The OMN loss directly affects PAE, e.g., 1 dB of OMN loss lowers the effective PAE of the output stage FETs by 20%. A secondary limitation of FET periphery is die size. The largest of the chip designs described herein are 5 mm by 8 mm. Larger ICs are more difficult to handle at the internal process of dicing and picking and the next level assembly process of eutectic die attach. The largest chip currently in production in MSAG is 64 mm².

An enabling capability of M/A-COM's MSAG P5A process is a variant called multilevel plating (MLP). This process variant allows the designer to employ two thick 4.5 µm gold metal layers for structures such as high-power transmission lines, high dc current carrying inductors and drain bus structures and a lower loss version of the typical gold on GaAs transmission line. These layers are implemented using interstitial layers of polyimide. When printed on a layer of polyimide then GaAs, the dissipative loss of a transmission line can almost be halved. The designs described in this paper are enabled by the MLP process and the structures that can be implemented as a result.

The evaluation of an MMIC amplifier is a lengthy multistep process that examines the performance of the device over frequency, temperature, input power, drain voltage, and bias point. Parameters collected include output power, drain current, gate current, harmonics, gain, noise figure, voltage standing wave ratio (VSWR), third-order intercept point (TOI), third-order intermodulation products (IMD3), fifth-order intermodulation products (IMD5) and spurious. This process is captured in the flow chart shown in Figure 4.

The evaluation of an MMIC amplifier in die form begins with the measurement of pulsed small-signal S-parameters tested over a wide frequency range, typically 10 MHz to 20 GHz. This testing often reveals stability issues that are not present or cannot be observed in the band of operation. These initial S-parameters are used to develop specifications for the first dicing of one or two of the wafers so that a more detailed characterization of the part can begin in connectorized test fixtures.

Power characterization is the first CW examination of the die product. This testing is performed over a drain voltage range, usually 4 V to 10 V; bias point: 105, 25% and 40% of IDSS; input power, small signal levels through 5 dB compression; and temperature. If no issues are found with the design, the results of this characterization are used in releasing the preliminary datasheet and determining the on-wafer production test plan. This test plan defines the test conditions of frequency, bias and input power, and lists the measurements to be performed, e.g., small-signal gain, large-signal power, gate bias and drain current. The remaining undiced wafers are screened using the newly developed production test plan.

Datasheets are transitioned from preliminary to final status when a statistically significant population of test data has been collected on a particular part. For die products, this data comes from on-wafer screening of a number of lots. Final data sheets establish min/max limits for parameters that are measured on 100% of the die product.

Following the power characterization, TOI and IM3 testing is performed under the same set of conditions as that of the power characterization. Shim-mounted die are used to measure the noise figure and CW S-parameters over temperature.

The primary test vehicle for performing the power and IMD characterization is the connectorized fixture shown in Figure 5. This fixture provides for improved grounding, excellent thermal management, and opportunity to adequately bypass the part. The die is eutecticly (80/20 AuSn) attached manually to a gold-plated CuW carrier. To this same carrier, 50 Ω input and output alumina substrates and 100-200 pF border caps are mounted. The carrier is then bolted into a brass fixture that includes RF SMA connector blocks, 0.01-0.1 µF capacitors to eliminate bias line instability, and dc connection points for bias application. During test, the fixture block is directly attached to an LN2 cold plate to maintain the required test temperature.

The high-power amplifier (HPA) MMIC measured results are summarized in Figures 6, 7 and 8 for saturated power output, small-signal gain and output 1 dB compression point (P1dB), respectively. These results were in-line with the simulation work that led to these designs. The designs were all found to be stable and free of spurious responses over extremes of temperature, voltage, input power and frequency. One goal for further development on these parts would be to improve gain flatness across the operating band, particularly for MAAPGM0077-die. The following paragraphs provide a brief summary of the performance of each die. The data sheet on the web site provides more detailed information.

MAAPGM0077-die is a two-stage 13 W 0.7 GHz to 2.5 GHz HPA with approximately 23 dB small signal gain that averages 41 dBm saturated and a 41 dBm 1dB compression point. It has been designed primarily for military and commercial communications.

MAAPGM0076-die is a two-stage 16 W 1.3 GHz to 2.5 GHz HPA with approximately 25 dB small signal gain that averages 42 dBm saturated and a 41 dBm 1dB compression point. Primary targets are military and commercial communications.

MAAPGM0078-die is a two-stage 12 W 2 GHz to 6 GHz HPA with approximately 20 dB small signal gain that averages 41 dBm saturated and a 40 dBm 1dB compression point. It is aimed at satellite and EW applications.

MAAPGM0074-die is a two-stage 8 W 2 GHz to 8 GHz high-power amplifier with approximately 14 dB small signal gain that averages 39 dBm saturated and a 38 dBm 1dB compression point. This HPA also eyes satellite and EW applications.

Unlike others, the MAAPGM0079-die is a three-stage 20 W 7.5 GHz to 10.5 GHz HPA amplifier with approximately 29 dB small signal gain that averages 43 dBm saturated from 8 GHz to 10 GHz and a 42 dBm 1dB compression point. The MAAPGM0079 has been designed for military and commercial avionics radar applications.

A thermal analysis has been run on these MMIC amplifiers using a spreadsheet based on Cook's model. This model provides as output a thermal resistance. With this thermal resistance, one can generate a maximum power dissipation curve that relates allowable quiescent (No RF) power dissipation, Pdiss = Vd * Idq, to the operating MMIC base temperature. This area below this curve constitutes the area of safe operation, i.e., the combination of power dissipation and MMIC base temperature will yield a channel temperature < 170 °C. Operation of this amplifier above this curve comprises device life. For the amplifiers described, the safe area of operation bounds are shown in Figure 9.

The die products described herein will soon be available in a new hermetic 10-lead ceramic flange-mount package. This package has a larger internal cavity to accommodate chip sizes up to 5 × 9 mm. This package was designed using EM and small-signal modeling techniques to operate up to 20 GHz. The base metal to which the die will be attached was designed such that the top surface of the MMIC and the package substrate are coplanar. This reduces the wire bond length (series inductance) used in the integration package/IC assembly and will aid performance in the X/Ku bands. A vacuum reflow process will be used to provide near-void free eutectic attach. Small value bypass caps will be integrated inside the package for improved stability. A ceramic lid with gold ring frame will then be eutecticly attached to yield a hermetic package. The packaged version of these dies are expected to be available by summer.

David Conway is product engineering manager overseeing MSAG MMIC test, layout, standard product development, customer support and service. He received his BSEE from Georgia Institute of Technology and his MSEE in Electromagnetics from the University of Southern California in 1984 and 1986, respectively. Conway joined M/A-COM in 2000 and has designed several 20 W S-band MMIC amplifiers.

Michael Fowler is an electrical engineer in applications for M/A-COM's Aerospace and Defense Integrated Circuit Products. He received a BSEET from Old Dominion University and is working on his Masters in Engineering Management from Old Dominion University. Fowler has five years of experience in application, design, systems and software engineering with M/A-COM.

Jack Redus is the product manager for M/A-COM's Microwave and Millimeter Wave MMICs focused on Aerospace and Defense applications. He received a BSEE from Rensselaer Polytechnic Institute, an MSEE from Santa Clara University, and an MBA from San Jose State University. Redus has 18 years of design engineering and product management experience related to microwave and millimeter-wave components.