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Mobile telephone handsets have witnessed a strong innovative drive to smaller and cheaper products with increased functionality and performance while still meeting the tight constraints for mass production within a short product life cycle. This combination of conflicting trends has been achieved by optimizing the key technical capabilities required in the development and production of each new handset generation.

In the baseband, advanced complementary metal oxide semiconductor (CMOS) integrated circuit (IC) processes have shrunk the silicon real estate required for the processor, memory and interface ICs.

Advanced chip scale package (CSP) techniques and multi-layer laminate printed circuit boards (PCB) with microvias have minimized the electronic interconnect and packaging volume. Battery technology has advanced from the older nickel cadmium and nickel metal-hydride to lithium ion and lithium polymer technologies, improving the battery pack size, weight and form factor.

The antenna has migrated from outside to inside the telephone plastic housing, giving more freedom in the telephone form factor and design.

The innovative improvement in the passive component content of a telephone has been much less dramatic compared to other technical areas. This inertia has not been due to a lack of attention by set-makers or in the literature.

For example, it is estimated that in a single-mode telephone, passive components account for 90 percent of the component count, 80 percent of the size and 70 percent of the cost. High-quality passive components are especially prevalent in the RF front end and radio transceiver sections of the telephone and thus tend to increase proportionally as the number of operating modes (and thus frequency bands) increase.

Indeed last year, 115 billion passive components were assembled into 380 million handsets at an average of 300 components per telephone. Of these, typically 100 to 150 are discrete passives in the front end and radio transceiver sections. In addition to dominating the component count, size and cost, the large number of passive components is a major factor in the assembly line production and yield and contribute to unwanted reliability failures in the field.

Methods to reduce the passive component content of a telephone have focused primarily on optimizing the system architecture and partitioning to increase the level of integration on the ICs without sacrificing the performance or cost. In the radio transceiver section, the move from a super heterodyne to a near-zero IF radio architecture eliminates the set of passive components required for the IF functions. This trend has been accelerated by the steady improvement in the performance of the passive components integrated in the RF IC processes, thereby enabling the integration of passive components on chips where previously only external SMD components could meet the required RF performance level.

A good example is the quality factor (Q) of integrated inductors. Values of Q up to 20 can now be achieved in state-of-the-art bipolar CMOS (BiCMOS) processes. This is due to the combination of improved metallization, thick dielectric layers and metal ground plane shielding. For many applications, this value of Q-factor is sufficient for the full integration of voltage-controlled oscillator (VCO) tank circuits on chip. Similar trends are seen in the performance of capacitors and varicaps.

A direct approach to reducing the passive component content in a telephone is passive integration technology. This technique allows several passive components to be integrated, either into a substrate or as a stand-alone component.

Despite its inherent simplicity, passive integration has received only limited application in mass production. A major obstacle to passive integration is identifying a suitable technology, which can encompass both the rich variety of passive component types required and cope with their scattered placement in an application. This is true even for the basic surface mount device (SMD) components.

For example, SMD film resistors can be made with intermetallic semi-amorphous alloys with a low thermal coefficient of resistance. Therefore, they can be laser trimmed to within 0.1 percent accuracy.

SMD inductors are optimized according to value and performance with either thin film, thick film or wire wound technology. High performance passive filters (e.g., SAW and dielectric) exploit surface or bulk material properties.

In contrast, a passive integration technology is built up from a multi-layer stack of a limited number of similar layers, which inherently limits the range passive component performance can be integrated. As an example, a dielectric layer with a particular specific capacitance density typically allows two to three decades of integrated capacitor value to be covered before it becomes either too small for the process technology or too large to be economically viable. The capacitance tolerance is a function of the process control of the dielectric layer and cannot be improved by component selection as with low tolerance SMD components.

Only a limited range of passive component types and values can be efficiently integrated in any passive integration technology. It follows that different technologies are suited for different applications depending on the match between the integrated passive component capability and requirement.

Passive integration is implemented in the RF front end of a telephone within modules used for radio functions around the transceiver and up to the antenna interface. In an RF module, the substrate is made either from low-temperature co-fired ceramic (LTCC) or a high-grade multi-layer organic (laminate) technology.

Because a module is relatively small and requires a specific RF function, there is more scope for economically integrating passive components in the module substrate than in the main board of the telephone. Both LTCC and laminate technologies provide a high density of distributed interconnect with well-defined ground planes. This makes it suitable for designing integrated inductor and stripline filter functions.

Laminate has the lower manufacturing cost and metallic loss, and is typically applied in power amplifier (PA) modules. However, the low dielectric constant (typical ε_r∼4) of laminate limits the range of integrated RF filter functions that can be achieved. LTCC has a higher dielectric constant (typical ε_r∼10) and with thinnest ceramic tape layers, capacitance densities of a few pF's/mm². Therefore they are sufficient for many RF diplexer and antenna filter functions. Furthermore, both LTCC and laminate technologies have typical layer thickness tolerances of ∼10%, which is reflected directly in the capacitance tolerance and performance spread of the RF component.

While LTCC and laminate are suited for integrating inductor and striplines, some RF functions require higher capacitance densities and lower tolerances than can be achieved within these substrates. For these functions, thin film passive integration technology is attractive because the thin-film processing is accurate and capable of achieving the higher capacitance densities and lower process tolerances required.

The complimentary attributes of LTCC or laminate on one hand and thin film passive integration on the other makes them a powerful multiple technology platform for increasing the level of passive integration within a module (see Figure 1). Furthermore, the higher manufacturing cost per mm² of thin film technology can be offset by partitioning the passive components between different technologies according to their size and performance. Thus, larger inductor and stripline components are integrated in the LTCC or laminate substrate. Small inductors and capacitors are integrated in a thin film passive integration IC.

Based on technology partitioning a thin-film passive integration IC technology on high-ohmic silicon has been developed. This particular process combines three metal layers and two dielectric layers in five mask steps to form integrated inductor and capacitor structures (see Figure 2).

Standard back-end IC process steps are used with a relaxed lithographic resolution (5 µm), which minimizes the manufacturing cost. The high-ohmic silicon substrate (ρ >5 kΩ/cm) combined with a clean interface to the first oxide layer ensures a minimal loss in the silicon substrate and a high quality passive component performance at RF frequencies. Furthermore, high-ohmic silicon wafers are available from wafer suppliers at similar price levels to normal low-ohmic wafers used for active ICs.

The integrated capacitors are formed by the 425 nm thick SiN_x dielectric layer between the lower two metal layers. The capacitance density of the layers is 145 pF/mm². The thick dielectric layer results in a lower capacitance density than in a standard BiCMOS process, but is required to reliably withstand the large peak voltages (∼30 V) at the antenna interface of a cellular telephone under extreme mismatch conditions. Good process control of the SiN_x deposition enables a low tolerance for the capacitance density of 3σ = 4% in production. This is significantly lower than in laminate and LTCC technologies.

Stripline inductors are formed from the thick 5 µmm aluminum top metal layer, which has a low inductance tolerance defined by the line width spread 3σ = 2 µmm. For multi-turn inductors, feed-throughs are realized with the bottom metal layer, minimizing the parasitic capacitance from the feed-through to the inductor turns.

This approach can achieve a high level of RF performance for the integrated components. Figure 3 shows (a) the measured quality factor Q of the stripline inductors and (b) the equivalent series resistance (ESR) of the capacitors. A high stripline inductor quality factor Q >50 is achieved with values Q >35 in the frequency range of 900 MHz to 6 GHz.

The Q factor is significantly higher than can be achieved in a conventional IC process and similar to inductors integrated in LTCC or laminate. The capacitor RF loss, given by the ESR <100 µW, is low compared to standard NP0 SMD components, which have a typical ESR = 300 µW. The combination of a low RF loss with a low production tolerance is the key to achieving high-performance, integrated passive circuits in applications.

Because the passive integration technology leaves little tuning possibility for the designer, accurate predictive simulation tools are vital to minimize the number of design cycles in development. The low loss, thin-film metal and dielectric layer stack used in this technology is well suited to commercially available planar electromagnetic simulation software such as Momentum or Sonnet. These tools are able to predict the passive performance of an integrated RF structure and the simulation results can easily be incorporated as S-parameter files into a circuit simulation environment.

ADS or Spice, for example, can be used to fully simulate the RF module performance. For passive integration structures, the level of accuracy of these tools is sufficient to realize first time right designs and speed up the product development cycle. The application of the technology in the output match network of a global system for mobile communications/digital cellular system/personal communications system (GSM/DCS/PCS) power amplifier module is shown in Figure 4. It shows the same module circuit composed of SMD passive components and striplines.

The function of the output matching circuit is to transfer the optimal load impedance of the final stage power transistor to the antenna impedance of 50Ω. To preserve the overall power added efficiency (PAE) of the PA and the output power level, the RF losses in the output matching circuit must be kept to a minimum. In addition, substantial second and third harmonic suppression of the non-linear power transistor should be realized to meet the application specifications. Further, the statistical spread of the PAE and output power due to component and production tolerances should be controlled to ensure a high production yield.

The circuit topology of the output match circuit is shown in Figure 5. The circuit has to offer a load impedance of 3Ω at 1.71 GHz, which is the lower end of the DCS band and transfer this to 50Ω. In the SMD component version of the matching network, the inductors are striplines LTCC and capacitors are 0402 SMDs. In the passive integration version of the circuit, only the critical small inductors and the matching capacitors are integrated onto the IC, while the larger inductors and the decoupling capacitors remain external.

This technology partitioning between thin film and the substrate allows the designer the flexibility to minimize the material cost of the RF function while still meeting the performance targets of the application. The simulated vs. measured input impedance of the output match circuit is shown in Figure 6. The agreement for the real part of the input impedance is good. For the imaginary part, there is an offset of 0.5jΩ in the simulation, which corresponds to about 50 pH at 1.71 GHz due to a small shift in the measurement reference plane.

The accurate simulation model of the output match circuit allows the production spread of the circuit to be calculated from the technology tolerances. The spread in RF performance comes not only from the IC but also from the wirebond assembly and the LTCC substrate.

In particular, the components at the low impedance end of the network (L_c1, C₁, L_c2, C₂) contribute most heavily to the total spread and need to be defined accurately. Using all the technology tolerances for a production environment, Figure 7 shows the results of a 500- point Monte Carlo statistical analysis of the simulation model for two frequencies. The scatter plot shows the spread in load impedance as seen by the power transistor that will result in a spread in the output power and PAE of the total module.

The module performance can be simulated by generating a load-pull model of the final transistor stage and fitting second order polynomial expressions for the module output power and PAE as a function of the complex input impedance. The obtained results for the output power are shown in Figure 8 for f = 1.71 GHz where the graph shows the number of occurrences of a measurement versus the measurement values. There is agreement between the simulated and measured spread in performance, which makes this a powerful tool for optimizing production yield.

Several key value drivers, other than the performance tolerance, need to be optimized in the design of the output match circuit. The module area occupied by the output match circuit is important for miniaturization. The output match insertion loss should be reduced to increase the PA efficiency. The material cost of the RF function should be controlled.

It can be seen (from Figure 4) that the wirebond assembly occupies a relatively large proportion of the total circuit area without performing a useful circuit function. The bond wires are actually an unwanted source of insertion loss and spread in the RF performance. As an improvement to wirebonding, flip-chip assembly technology provides a much cleaner and more compact interconnect between the die and the module substrate (see Figure 9)

Higher frequency communication standards require a tighter performance of the passive components due to the relatively stronger effect of parasitics at these frequencies. Passive integration is an ideal platform due to the low interconnect parasitics between the integrated passive components and the small tolerance on the component values.

The concept of technology partitioning within an RF module platform to optimize size, cost and performance can be extended beyond integrated (L,C) circuits. Thin-film techniques are advancing to encompass more functionality on high-ohmic silicon, which remains an excellent integration substrate due to its low RF loss factor and its suitability for mass production.

Sol-gel deposition of ferroelectric insulators enables the integration of high capacitance densities (>10 nF/mm²) required for low frequency decoupling.

Accurate deposition of multilayer dielectric stacks enables the integration of bulk acoustic wave (BAW) resonators for highly selective filter functions.

Anisotropic and sacrificial layer etching enables the integration of micro-electro-mechanical systems (MEMS) for miniaturized switching elements.

Decoupling, filtering and switching are all electrical functions which can not be effectively integrated on active silicon and which are required in the generic circuit blocks which form the RF front end of a radio transceiver (see Figure 10).

Passive integration into partitioned circuit elements and their combination within an RF module platform provides a unique and powerful tool for minimizing the passive component count within a cellular telephone and is a key enabler for developing smaller, cheaper and more powerful wireless products suitable for mass production.

The author acknowledges the valuable contributions of many people to this work including Freek van Straten, Pieter Lok, Arnold den Dekker, Jan-Willem Lobeek, Stephane Bertonnaud, Remco Ooijman, Johan Dijkhuis, Anh Hoang and Joost van Beek.

Nick Pulsford is Bluetooth program manager at Philips Semiconductors, responsible for Bluetooth and WLAN module pre-development. Pulsford graduated in physics in 1986 and received his D.Phil for the Optical Studies of Semiconductor Superlattices in 1990 from Oxford University, England. After a two-year Royal Society fellowship at the Max-Planck-Institute für Festkörperforschung in Stuttgart, he joined Philips Research Laboratories in 1992. Pulsford's main interests ranged from semiconductor material properties to thin-film passive integration resulting in more than 40 conference and journal publications. In 1999, he joined Philips Semiconductors where he introduced passive integration technology. He can be reached at nick.pulsford@philips.com