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The wireless marketplace is experiencing a technological transformation. Features that were once only dreamed about are now, or soon will be, standard on the wireless handsets of today and tomorrow.

Existing products currently include voice-mail, paging, e-mail, MP3, PDA, rudimentary Internet browsing and voice recognition. Future 3G products will implement a more sophisticated browser, digital camera, streaming video, and GPS functions with real-time mapping.

To support consumer growth and demand, handsets are incorporating higher processing bandwidths. Staggering processor throughput forces memory manufacturers to develop increasingly sophisticated products tailored to the needs of the wireless marketplace.

Wireless manufacturers demand low-priced memories with low power consumption, high-speed operation and high density, all in a small package size. The last four characteristics are virtually equal in significance, but the price of the memory is paramount.

Wireless handsets are especially price-sensitive because cell phones are often provided to the end customer at a steep discount to encourage enrollment. Recent trends in dynamic random access memory (DRAM) and Flash memory devices target performance and price in the wireless handset market.

One goal of portable design is to maximize battery life. Extending the time between battery charges needs to be balanced with the pressure to add new, energy-consuming features. The move to use color LCDs and the increased processing bandwidths required when performing sophisticated compression/decompression algorithms are examples of trends adding to battery demands. Improving battery technology and reducing power consumption in the system subassemblies are solutions. Memory manufacturers have embraced this challenge by developing products that minimize power consumption while simultaneously increasing READ/WRITE throughput.

A consideration when developing low-power memory products is the usage profile of a typical 3G terminal product (see Figure 1). In a typical profile, the memory subsystem is normally in sleep mode waiting for an interrupt to launch a new operation. Idle periods occur when the processor is performing a function but not interacting with the memory subsystem. The active period occurs when accessing the memory. When the system is in sleep or idle modes, the memory devices are in a low-power, standby state. The ratio between active and standby modes is roughly 40 to 1. This ratio suggests, as do active and standby current levels, which operational mode to target for optimization. This enhances low-power performance.

Low-power Flash products have active currents on the order of 20 mA and standby currents typically in the 20 mA range. This 1,000-to-one ratio indicates that the power consumed during the active mode exceeds dissipation during standby operation. Flash products focus on high-speed architectures that increase the read bandwidth, which simultaneously decreases the active period and minimizes the total (active + standby) power consumption.

DRAM products do not have an active-to-standby ratio as pronounced as Flash devices. DRAM devices consume substantial amounts of power during standby periods because of the self-refresh necessary to ensure data integrity. New DRAM offerings are focusing on methods to minimize the power dissipated during self-refresh.

Memories with high-speed page- or burst-mode access are rapidly displacing the legacy asynchronous interface. These newer memories capitalize on adjacent memory locations that are more readily available than random accesses. The initial access for a page- or burst-mode memory takes the same amount of time as a traditional asynchronous device, but subsequent addresses can be read at a much faster rate. These high-speed modes of operation are most effective when the host processor fills a cache line. Migrating from asynchronous to page mode, and recently to synchronous architectures, allows for significant savings in power consumption. The reduction in time spent accessing data results in minimizing the time spent in the high-power active mode. Figure 2 describes the timing of asynchronous, page and fully synchronous (SDRAM) READ operation.

Page-mode products provide improvements in average throughput without requiring significant changes to the memory controller. A page-mode READ access is initiated by enabling the device and specifying the desired access. Once the first data value is output, subsequent (adjacent) addresses may be read by changing the lower-order address values. The lower-order two or three address lines are toggled to access adjacent data values. The initial access takes the same amount of time as an asynchronous device, but subsequent accesses within the page occur more rapidly.

Synchronous burst products further reduce the time spent in the high-current active state. A typical 100 MHz SDRAM can burst eight addresses in 130 ns. A 60 ns period is required to access the initial address, and then each subsequent address requires an additional 10 ns (see Figure 2). On the other hand, a 60 ns asynchronous SRAM device requires 480 ns to access eight addresses.

Figure 3 describes the relative performance of different Flash memory architectures. As data transfers increase in length, the average read bandwidth improves. Longer burst lengths (>eight addresses) are rare in most of today's applications, but the ability to pipeline burst operations becomes increasingly useful as memory controllers become more sophisticated.

Figure 3 also demonstrates the superior performance of the Flash burst and the SyncFlash (SDRAM) burst interface when transferring four or eight addresses. These burst lengths are significant because most cache lines are the same size. The increased transfer rate directly affects system performance in the event of a cache miss.

Figure 4 describes the average energy expended during a typical read operation when filling a cache line (eight words). Note that the speed of the SyncFlash product effectively offsets its much higher current consumption when compared to other 3.0 V products. Burst-mode Flash products have been specifically developed for the wireless marketplace. These devices require a 1.8 VDC operating voltage and provide an impressive read bandwidth while consuming a modest amount of current. The burst-mode product has been widely accepted and will likely dominate in the future.

Next-generation products will not only include more functionality, but will also come in increasingly smaller packages.

Today's cell phone can easily fit into a pocket. Tomorrow's 3G terminal products will also cause memory manufacturers to field increasingly smaller packages. This reduction in handset size causes memory manufacturers to field increasingly smaller packages. Packaging for wireless memories has quickly migrated from plastic leaded-chip carriers (PLCCs) to thin, small-outline packages (TSOPs), to ball-grid arrays (BGAs), to stacked die BGA and, in the near future, to system-in-package (SiP) technology.

Fine-pitch ball grid array (FBGA) packages have been available for some time. This packaging technology is a printed-circuit-board substrate where a die is attached. Bond wires are used to connect the pads on the die with the traces on the substrate. The backside of the substrate incorporates a matrix of solder balls used to attach to the host printed circuit board (PCB). Today's packages for wireless applications typically use a 0.75 mm or 0.8 mm ball pitch with many products still available with 1.0 mm and 1.27 mm spacing. Considerable pressure in more sophisticated applications exists to migrate to a 0.5 mm ball pitch. The more aggressive spacing will become increasingly common in the next few years as assembly-related issues are addressed.

Additional savings occur in PCB real estate when SRAM and Flash devices are assembled in the same package. This “combo” approach typically implements an SRAM die physically bonded to the top of a Flash die on an FBGA substrate. Address and data buses are common to both die with the power and control lines bonded out separately (as required) for the Flash and SRAM devices. The combo package often results in a slightly larger footprint (typically < 20% increase) to accommodate the additional bond wires. The height of the package also increases slightly to accommodate the second die.

The next step in footprint reduction is to mount multiple die on a common substrate. This technology is referred to as multichip module (MCM) or SiP. A processor(s) and its required memory are candidates to fit into this paradigm. This configuration allows for an isolated memory bus that dramatically lowers inter-die bus capacitance. The reduced bus capacitance minimizes power consumption during memory access. The peripheral (non-memory) interface routes to the balls on the SiP substrate. The substrate is part of an FBGA package and significantly reduces the footprint required by the equivalent individual FBGA components.

Advances in assembly technology are opening even wider possibilities with new die stacking, bonding and interconnection technologies. These technologies are not only reducing footprints, but enabling performance gains with shorter interconnect distances.

Price and density pressures in the wireless world make cost-effective DRAM technology attractive. Existing 6T SRAM products become prohibitively expensive at the 16 Mb density, and DRAM offerings have been developed as an alternative to 6T products. Next-generation wireless designs are requiring as much as 256 Mb of READ/WRITE memory. At these densities, DRAM technology provides a practical solution.

Traditionally, DRAM technology has required high self-refresh currents to maintain data integrity. 6T SRAM standby currents are less than those required by DRAM products of similar densities. While 6T SRAM has superior standby current consumption, DRAM offerings are focusing on architectural features that minimize the impact of self-refresh operation.

One emerging product category implements an SDR SDRAM that allows system control over self-refresh operation. In these new devices, self-refresh operating characteristics are altered to minimize standby currents. Self-refresh is enabled to the extent required to adequately sustain data integrity. Two features of particular interest are partial array self-refresh (PASR) and temperature-compensated self-refresh (TCSR). PASR is used to restrict self-refresh to only that part of the memory containing vital data. Non-refreshed regions will quickly become corrupted and should not be considered for data storage. Reducing the number of refreshed cells has a direct impact on the self-refresh current consumption levels. TCSR takes advantage of the fact that to maintain data integrity, refresh needs to occur more frequently as the operating temperature rises.

Standard DRAM products typically refresh the entire array every 64 ms, adequate for the worst-case (highest) temperature. Operation will normally occur at more moderate temperatures. TCSR allows the system to reduce the self-refresh rate as temperatures decrease. Existing devices typically have settings for operation at four temperature ranges. PASR and TCSR are now standard Electron Device Engineering Council (formerly the Joint Electron Device Engineering Council — JEDEC) features for low-power SDR SDRAM products.

Pseudo-SRAM (PSRAM) products have been introduced as solutions for low-power applications. PSRAM devices incorporate a traditional asynchronous SRAM interface, but use high-density DRAM technology for the memory array. These devices implement a self-refresh virtually transparent to the host system. The transparent refresh is made possible by extending the period specified for a READ cycle to include time for both a refresh operation and a READ operation. The same scenario also applies to the WRITE cycle. This doubling of the cycle time guarantees that refresh can successfully be scheduled in any well-designed system. Because these products have no legacy DRAM counterparts, they have been designed specifically for low-power environments. The DRAM array is designed with small partitions to minimize the active current during READ and WRITE cycles. Another low-power feature is the redefinition of the second-chip enable (CE2) pin found on legacy SRAM products to facilitate a deep power-down state. The redefined pin allows the system to stop all internal self-refresh operations and places the PSRAM device into a low-power state that draws only a few mA of standby current. Placing the PSRAM device into deep power-down will cause data corruption and is only used when essential data can be stored elsewhere. PSRAM devices have largely followed the legacy asynchronous SRAM interface. Today, manufacturers are implementing PSRAM variants targeting the wireless marketplace.

Existing memory controllers include support for the legacy asynchronous SRAM interface, allowing rapid acceptance of PSRAM products. As density and bandwidth requirements continue to climb, pressure will be increasing to support high-density, high-performance SDRAM products. Several chipset manufacturers are already developing memory controllers that fully support the JEDEC-standard, low-power SDRAM interface. SDRAM, or other high-speed synchronous memory interfaces, will likely displace the legacy asynchronous SRAM interface over the next several years.

The role of Flash memories has changed over the past few years to include the ability to store multiple applications and large amounts of data.

Embedded operating systems, support for multiple wireless protocols, sophisticated applications software and Flash file systems have placed increasing demands on Flash products. Flash arrays are now partitioned to more easily facilitate the storage of data. Older devices prohibit array READ operations during program and erase operations. Newer products partition the array to allow a READ operation from one area while performing an ERASE or PROGRAM operation on another section.

Flash memories have also evolved to embrace a high-speed synchronous interface. A burst-mode READ operation is included on newer NOR-based Flash devices targeting the low-power market. These offerings include the legacy asynchronous READ/WRITE operation and also support page and burst-mode operation. Switching between the different READ modes is accomplished with the use of an on-chip mode register.

Flash devices have migrated to a 1.8 VDC operating voltage and are expected to reach 1.5 VDC in the near future. Higher data throughput requirements create the need for more sophisticated burst interfaces. SDRAM operating frequencies are roughly 50% faster than standard wireless Flash.

The countless permutations possible with the various architectural options and operating voltages leads to a fragmented marketplace for wireless Flash products. This market is characterized by several of the leading wireless companies working closely with Flash manufacturers to co-develop next-generation products. Once developed, the most successful of these product offerings will be available for general consumption.

As wireless processing requirements continue to escalate, memory manufacturers will develop new devices targeting this demanding environment.

DRAM technology is a viable alternative because density requirements have increased to the point where moderate standby currents are acceptable. Flash products have developed high-speed interfaces that provide bandwidths on par with synchronous DRAM devices. Memory interfaces will continue evolving to support consumer growth and demand for more sophisticated features.

Cliff Zitlaw is an applications engineer with Micron's Wireless Products Group. Before joining Micron, he worked for eight years as a consultant developing evaluation platforms for various nonvolatile memories.