Silicon Laboratories Inc. has entered the frequency control market with a line of crystal oscillators (XOs) and voltage-controlled crystal oscillators (VCXOs) for applications up to 1.4 GHz. Leveraging its patented third-generation DSPLL technology, these series include the industry's first quad frequency XO and VCXO devices (see figure), claimed Silicon Labs. In addition, the Si550 and Si530 families provide the industry's shortest lead times, highest reliability and best performance, making them suitable for networking equipment, base stations, test and measurement equipment, storage area networks and video systems.

Silicon Labs' DSPLL approach simplifies clock multiplication and jitter attenuation circuitry required in high-speed telecom applications. It is considered the standard approach for replacing multiple discrete phase-locked-loop (PLL) components with a single IC that integrates digital signal processing (DSP) circuitry and an ultra-low jitter voltage-controlled oscillator.

With optimized DSPLL technology, the company is able to move frequency control and tuning from a complex resonator to a single CMOS IC, enabling the Si530 and Si550 families to deliver total frequency stability over time and temperature that is more than two times better than traditional high-frequency, low-jitter oscillators. DSPLL-based frequency tuning also enables up to a tenfold improvement in initial frequency accuracy when compared to designs based on traditional high-frequency SAW or crystal resonators, asserted the manufacturer.

“Silicon Laboratories' market-leading jitter performance challenged our best jitter measurement test system,” said Amir Aghdaei, vice president of Agilent's Worldwide System Solutions Division. “We developed the JS-500 with very low intrinsic noise, great clock rate flexibility and true continuous peak-to-peak measurements to help Silicon Laboratories verify its DSPLL-based products' unmatched jitter performance metrics.”

The Si530 and Si550 families leverage the frequency synthesis capability of a mixed-signal IC to eliminate complex materials processing steps required to frequency tune traditional SAW and crystal-based implementations. This simplifies the manufacturing process and reduces lead-times from eight weeks to one week.

“Traditionally, PLL technology has not met the jitter and phase noise requirements for clocking networking and telecommunications applications,” said Scott Smyser, director and principal analyst of iSuppli Corporation. “A high-performance, low-noise PLL brings increased flexibility, performance and reliability to designers that was not previously available from high frequency oscillator technology.”

Based on 0.13 micron CMOS with non-volatile memory, the XO and VCXO families support operation over a frequency range from 10 MHz to 1.4 GHz with less than 0.3 ps rms jitter. The Si530 and Si550 families also offer improved control voltage linearity while providing a wide selection of voltage gain and pull range options giving more flexibility to a designer when choosing the device for the application.

“Today, high-frequency, low-jitter oscillators are based on complex resonator technology that forces system manufacturers to endure long, unpredictable lead times and incur significant costs in qualifying and monitoring the reliability of these devices,” said Brad Fluke, vice president of Silicon Laboratories. “We are excited about applying our DSPLL technology to the problems associated with the high-frequency oscillator market while introducing new levels of functionality.”

Housed in an RoHS-compliant, 7 mm × 5 mm surface-mount package with support of common output formats: PECL, LVDS, CMOS and CML, the Si530 and Si550 are sampling with production scheduled for the fourth quarter.

For more information, visit www.silabs.com