With the introduction of new resistance and capacitance engines for its full-chip, transistor-level parasitic extraction solution, Calibre xRC, EDA vendor Mentor Graphics Corp. has introduced a simulation technology for nanometer silicon designs.

Based on the new resistance engine, Mentor Graphics has also developed hierarchical netlisting and optimized back annotation capabilities between Calibre xRC and Nassda's high-performance simulation platform HSIM^plus.

“Our designs require the most sophisticated methods available to model the behavior of advanced manufacturing technologies,” said Karl Johnson, senior CAD engineer, Centaur Technology. “Calibre xRC, coupled with Calibre LVS (layout vs. schematic), allows us to accurately and efficiently capture the 90 nm effects and deliver data to our downstream timing analysis and signal integrity flows at both the gate and transistor level.”

The shrinking geometries and increased design sizes prevalent today have created greater chip functionality but have also taken some of the predictability out of modeling at the device level. For example, to accurately model the behavior of a transistor, the number of parameters has grown significantly beyond simple length, width and area. Nanometer effects can cause an entire chip to fail and must be correctly accounted for in post-layout simulation and analysis to ensure acceptable yield. Calibre xRC's new resistance and capacitance engines, combined with Calibre LVS, fully comprehend the boundary of the BSIM4.0 simulation model to accurately measure, extract and analyze these new parasitics in a geometrically accurate way with smaller netlists, helping to preserve performance, capacity and yield.

Calibre xRC's new resistance and capacitance engines offer several advantages. The resistance engine provides better fracturing, including precise width and resistor location for electro migration analysis. It also offers enabling technologies for inductance extraction and improved device pin handling, improved gate pin placement and user control over gate region extraction. Additionally, the algorithms are hierarchical and more efficient. Better performance and capacity are attained using the new paradigm while still providing improved accuracy.

Calibre xRC's new capacitance engine delivers a tighter correlation to field solver and silicon data, improving overall accuracy of results. In addition, it has incorporated special models for vias, contacts and the poly-to-contact area, as these are susceptible to significant and elusive capacitance effects. Other solutions are taking mathematical shortcuts to modeling that will get them quick extraction results but will break down later in the design flow. Calibre xRC gives designers greater confidence in their post-layout simulation results and, therefore, they do not have to build-in prohibitive design margins.

“A comprehensive approach to nanometer silicon modeling is an essential part of a complete DFM design flow,” said Joe Sawicki, vice president and general manager, Design-to-Silicon Division, Mentor Graphics. “Based on silicon results, we are confident that Calibre's new resistance and capacitance engines address yield limiting factors in nanometer technology.”

The collaboration between Mentor and Santa Clara, Calif.-based simulation and analysis solutions provider Nassda gives designers the ability to efficiently simulate large, complex nanometer designs. Calibre xRC DSPF data structures and extraction algorithms, optimized for Nassda's preferred flow, enable users to experience high degrees of accuracy and performance.

For more information, visit www.mentor.com.