Around since the late 1980s, software-defined radios (SDRs) are making the transition from advanced military and intelligence applications to satellite and cellular systems and will soon reach mainstream consumer applications.

Besides its military applications in such programs as Speakeasy, the Airborne Integrated Terminal Group (AITG) and the Joint Tactical Radio System (JTRS), software defined radios are also used in such commercial applications as cellular radio base stations (by far the largest application) and the FAA's next-generation digital VHF system.

They are also under consideration to provide interoperability between legacy land-mobile systems and APCO25. Soon, SDRs will appear in automobiles with multimode AM/FM/XM satellite radio a possibility.

In broad terms, a software-defined radio is any radio where the signal chain is partially software. In practical terms, it will have some or all of the following features:

• wideband (WB);
• multiband (MB);
• multimode (MM);
• multi-rate (MR);
• the ability to be reconfigured by software; and
• a data converter as close to the antenna as possible on both transmit and receive.

Figure 1 shows a generic software-defined radio.

Many of the functions can be implemented in analog or digital form — the choice of implementation is, as always, a tradeoff between the availability of components, complexity, and cost.

Typical elements of a software-defined transmitter include:

• software-implemented error correction coding and modulation, and hardware-implemented digital upconversion;
• digital-to-analog conversion (DAC); and
• analog upconversion.

The software-defined receiver includes:

• analog downconversion and filtering;
• analog-to-digital conversion (ADC);
• digital downconversion and filtering and software-implemented filtering;
• demodulation; and
• error-correction coding.

The programmability of the radio is what allows the user to use it as a multiband, multimode transceiver, with such modes as:

• amplitude modulation (AM);
• single side band (SSB);
• narrow band frequency modulation (NBFM); and
• both two- and four-level frequency shift keying (FSK).

The challenge is designing transmit and receiver hardware that provides, as closely as possible, a linear, time-invariant system that provides a “clean” input signal to the digital signal-processing hardware so that a common signal chain can be used for all modes of operation under software control.

That is, the receiver architecture is based upon the choice of ADC, which dominates the available dynamic range.

A single ADC can over- or under-sample the modulated signal, performing a down-conversion in the process, and, with 4x sampling, provide I and Q outputs.

However, the higher the frequency sampled, the more the effects of aperture uncertainty, due to clock jitter, erodes the effective number of bits. Thus, there is always an inherent trade-off between speed and resolution.

The single ADC can be followed by a digital downconverter with numerically controlled oscillator (NCO) implemented as a field programmable gate array (FPGA) or receive signal processor (a dedicated digital chip), which may also filter and decimate the signal before it arrives at the digital signal processor (DSP) for demodulation.

Conversely, using an analog demodulator with analog baseband in-phase (I) and quadrature (Q) outputs relieves the burden on the ADC and allows additional passive filtering at baseband to reduce the required dynamic range.

The drawback is that it introduces quadrature imbalances due to phase and amplitude mismatches in the I and Q channels. It also requires two matched anti-aliasing filters (which may double as channel filters) and matched ADCs (or matched S/H amplifiers and a single ADC).

Another design tradeoff is between analog and digital filtering. Passive analog filters have low intermodulation distortion and consume no power, but they do have group delay, occupy considerable board space, especially at low frequencies, and there is always a tradeoff between cost, bandwidth, and Q.

Digital filters can be designed with near-ideal performance, but also have a speed-power tradeoff — more taps or a higher operating frequency require more millions of instructions per second (MIPS) in a DSP, dedicated hardware in an FPGA, or a purpose-built chip called a receive signal processor, which can provide downconversion, decimation, and filtering.

The dynamic range of the ADC is the fundamental tradeoff between analog and digital filtering: more analog filtering reduces the ADC's required dynamic range and passive filters do not consume power, whereas more digital filtering increases the ADC's required dynamic range but digital filters can have near-ideal characteristics.

For the system to be linear, the ADC must accommodate the desired signal plus interferers plus margin for fading and automatic gain control (AGC) response time. The calculations for determining the ADC's dynamic range must include:

• the mode-dependent carrier to noise ratio (C/N) for demodulation;
• overhead for such interferers as adjacent, alternate, and co-channel; and
• PA feed through (in full duplex systems), fade margin, and overhead for the AGC's response time to prevent receiver “blinding” when AGC system responding to change in input level.

In general, wideband receivers incorporate more of the dynamic range in the ADC and have less overall gain (˜35 dB) and a lower AGC range (˜10 dB) than narrowband receivers.

System design also includes both a cascaded noise figure and intercept analysis and frequency planning. Frequency planning is an art in and of itself, but basically the designer must minimize external and internal interference by careful selection of system clock, intermediate frequencies and local oscillator frequencies.

No discussion of frequency planning would be complete without a mention of the system clock. The system clock is usually a “magic number,” that is, a multiple of the frame rate of the encoded data. It is also often a multiple of the channel spacing to allow the use of integer N phase-locked loops (PLLs).

A complete design also includes full system calculations for minimum and maximum input signal levels, with one set of calculations for minimum input signal with AGC off, that is, no gain reduction, and one set of calculations for maximum signal level, that is, AGC full on, with maximum gain reduction. It also includes inter-modulation distortion (IMD) effects at both minimum and maximum signal levels.

One subtle point in system design is the AGC system. In a software-defined radio, AGC keeps the system linear by reducing gain for large signals. The AGC threshold is set so that C/N increases linearly until some optimum C/N is reached, then the gain reduced, generally dB per dB of increase for constant input into ADC.

The AGC threshold is also set to allow headroom in ADC so that AGC system has time to respond to rapid chances in input signal and avoids overload. There are two basic implementations for AGC — feedforward and feedback.

A typical feedforward AGC system measures the input signal — usually at intermediate frequency (IF) — with a log amp and sets the downstream gain to maintain a constant signal level at the AGC. It is the fastest responding gain system, but may need calibration since it depends on the accuracy of both the log amp and the scale factor (typically dB/V) of the variable-gain amplifier.

A typical feedback AGC system compares the detected signal to a reference and uses feedback to keep the detected signal level constant. The system should have fast attack (gain reduction), slow decay (gain increase) AGC time constants. It requires linear-in-dB gain for a stable feedback loop. Signal path latency can allow receiver to be blinded by strong signals, especially with digital AGC.

For example, using analog AGC with a peak detector at IF, it takes some number of cycles at IF to charge AGC capacitor before the feedback is valid.

Using a detector at baseband and calculating the signal level value from I and Q baseband values works in either analog or digital domains, but has worse latency than IF derived AGC, especially when calculated in digital signal processing (DSP).

The PLL's settling time when changing frequencies must also be taken into account, as this time delay introduces latency throughout the system. For example, the time to change frequencies must include the PLL's settling time, AGC response time, time for the signal to travels from the antenna to ADC, ADC conversion time, and signal processing time in the DSP.

Coherent demodulation in the DSP is the most complex architecturally, but the best performing. See Figure 2.

The matched filter is usually a maximum likelihood detector (MLD), or a squaring/quadrupling detector for binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK), respectively. If the extra processing of the MLD can be handled, the gain in low signal tracking performance could be 6 dB or higher. In many instances, both carrier and clock are recovered by PLL.

The input is typically oversampled and stored in a circular buffer. The read index to this buffer is the output of the clock loop filter via the NCO. Alternatively, an interpolator or direct sampling via an ADC can be used.

Next, complex mixers (at baseband) distinguish between positive and negative frequencies. They also have the advantage of not needing low-pass filtering to remove mixing products. The output of the mixers feed a matched filter block, which uses a maximum likelihood detector. Each incoming waveform is correlated with each possible incoming waveform. The largest correlation is selected as the most likely received waveform.

For waveforms that contain memory, such as minimum shift keying (MSK), the matched filter block should use a trellis approach to achieve maximum bit error rate (BER) performance. Instead of choosing the largest correlation directly, each correlation can be used as a branch metric for a Viterbi algorithm with the best survivor used as the most likely received waveform.

Care should be used in selecting the traceback length in order not to introduce excessive delays into the recovery loop. For modulations requiring longer traceback, the recovery loops may use a shorter traceback than the data decision.

The carrier phase detector block computes a derivative with respect to phase of the incoming waveform's correlation with the most likely reference waveform. This phase detector has a 3 dB advantage over a traditional phase shift keying (PSK) squaring loop detector.

The order of the loop filter block indicates the type of error the loop can recover perfectly.

A first-order loop will have a steady-state error response to a frequency step. A second-order loop can recover a frequency step perfectly, but will have a steady-state error response to a frequency ramp. A third-order loop may also be used where perfect recovery of a frequency ramp is required, however, care must be taken to avoid instability problems as a function of input gain.

The type indicates the number of perfect integrators in the loop. The NCO is one integrator and the loop filter will contain the rest.

The first-order filter is, by default, a type-I with no integrators in the filter. A second-order filter can be a type-I “leaky” integrator or a type-II “perfect” integrator. Note that the second-order type-II has infinite memory in its perfect integrator and, therefore, no restoring force back to zero. It must, therefore, be clamped to a maximum and minimum value.

The carrier NCO block generates a sine wave that has a frequency proportional to the input value. Built-in C trig functions of sin() and cos() may be used, but are time consuming. Table look-ups may be used instead to increase speed of execution at the expense of phase quantization noise.

The design of the clock phase detector block depends on the type of modulation. Because there is no closed-form solution for the time derivative of the matched filter correlation, clock phase detectors are modulation dependent.

BPSK and frequency shift keying (FSK) demodulators typically use a technique called an early-late gate. This is implemented by integrating over the symbol transitions ±Ts/2.

MSK and continuous phase modulated (CPM) modulations can use a manipulated version of the carrier phase detector output as a clock phase detector. This is due to the fact that the waveforms are sinusoidal and the time derivative is proportional to the phase derivative by a data-dependent constant.

So, is all of this work worth it?

For a single-mode radio, probably not.

But if the design goal is multimode operation with the ability to download software upgrades, then most definitely yes.

Likewise, if you need backwards compatibility with legacy radios or interoperability among different vendors, then software is the way to go. And as converter and digital signal processing technology improves yearly, the power versus performance tradeoff will continue to improve.

Robert Clarke is a field applications engineer at Analog Devices Inc. (www.analog.com), and has a B.S.E.E. from the Massachusettes Institute of Technology.

Kevin Kreitzer is also a field applications engineer for Analog Devices.

• What does the standard require?
• What does the receiver's input spectrum look like?
• What are the desired signal min and max levels?
• What are the desired adjacent, alternate, and co-channel interference levels?
• How much analog filtering is needed?
• What is the signal bandwidth?
• What Image filter, channel filter, and anti-aliasing filters are available?
• Is group delay an issue?
• Does it affect filter choices?

• Digital filters are better than analog filters — so this is a big system tradeoff.
• Analog filters with low group delay cost big bucks.