Sumio Ogawa and Minoru Ueki, both of Higashihiroshima, Japan, and Shinichi Hara of Shimonoseki, Japan, have developed a semiconductor device manufacturing system for determining the cause of failures in a semiconductor device.

According to the U.S. Patent & Trademark Office, “A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package.”

An abstract of the invention, released by the Patent Office, said: “A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.”

The inventors were issued Patent No. 7,054,705 on May 30. The patent has been assigned to NEC Electronics Corp., Kanagawa, Japan.