Some of the latest mobile handsets feature up to four additional frequency bands, and they are pushing the limits of performance available with traditional technologies. The switching function that connects all of these frequency paths to the antenna has been of special interest because of the increasing complexity and demanding RF performance requirements of 3G and emerging 4G systems. UltraCMOS, a silicon-on-sapphire technology, shows promise for developing these new, complex switching products.

The GSM platform became the dominant global mobile technology without the same stringent oversight that drove other handset platforms. Handset manufacturers continue to take advantage of GSM's greater flexibility in terms of architecture, performance and functionality. In recent years, as the 3G mobile handset market began to migrate to wideband CDMA (WCDMA) in order to support Internet, multimedia and video features, GSM has responded by evolving into a dual GSM/WCDMA technology. In order to satisfy worldwide travelers and requirements, GSM phones can have up to four transmit (Tx) and four receive (Rx) paths. Adding WCDMA functionality requires an additional Tx/Rx path for each new band. The current design trend is toward 4xGSM (850 MHz, 900 MHz, 1800 MHz, 1900 MHz) and 3xWCDMA (850 MHz, 1900 MHz, 2100 MHz) front ends, which is pushing handset complexity to record levels. For designers of the RF front end, which includes the antenna switch module (ASM) and the power amplifier (PA), this scenario can translate into significant architectural, performance and cost challenges. Any design trade offs have to be made with an eye on performance, however, because as complexity increases and GSM specifications are merged with those of WCDMA, simultaneously delivering on both technologies' specifications becomes critical.

Given the proximity of the adjacent Tx band, two PAs typically handle GSM/DCS while an additional PA is required for each WCDMA band. In the end, the architecture of a quad-band GSM phone with one WCDMA band requires a single-pole, seven-throw (SP7T) switch. Alternatively, it is possible to use a diplexer and a combination of an SP3T and SP4T (a popular GaAs configuration), but this results in higher insertion loss than when using a single SP7T switch. Insertion loss is a critically important specification because it directly impacts the effective power-added efficiency (PAE) of the PA as well as the overall system noise figure. GSM PAs are typically run in saturation at up to 2 W, and their average PAE is 60%. This level of efficiency is necessary to ensure battery life, since half of the total handset current drain is from the PA. As a result, degrading the PA's PAE is not desirable.

The latest triple- and quad-band GSM systems are especially challenging to design because the GSM Tx band overlaps with the GSM850 Rx band, and the PCS Tx band overlaps with the DCS Rx band. During transmit, the Rx band select filters do not provide any attenuation to the transmitted signal that leaks through the switch. So, in order to protect the low-noise amplifiers (LNAs) that follow the Rx filters, the switch must inherently provide at least 35 dB of isolation.

The WCDMA standard requires high linearity for the RF front end. Because it is usually connected directly to the antenna port, the antenna switch must be linear enough to cope with any unwanted outside signals. To further complicate things, since the front-end switch does not have any filtering, it must have high electrostatic discharge (ESD) tolerance, either inherently or through additional protection circuitry. For example, handsets must survive ±8 kV contact discharge and ±16 kV air discharge per the IEC IEC 61000-4-2 specification.

After all of the technical requirements have been addressed, there are still the additional constraints of size and cost to consider. Height requirements within mobile handsets are dropping below 1.4 mm, and industry-standard form factors have been established for a roadmap of size reduction. Technologies that can shrink ASMs are badly needed because they are typically the tallest devices in the radio section.

There are several available switching technologies that can be used in GSM and WCDMA handsets, each with its own advantages and disadvantages. Still the dominating technology in ASMs since their introduction in the 1970s, PIN diodes are prized because they achieve very low insertion loss and very low harmonic distortion. However, to bias the diodes, the module must include blocking capacitors and feed inductors. To build a multithrow switch, series and shunt diodes are combined by quarter-wave transmission lines (Figure 1a) which dictate the size of diode-based ASMs.

GaAs pHEMT switches (Figure 1b) are a viable replacement to PIN diodes, and they reduce the size and complexity of ASMs. However, design challenges remain. For instance, GaAs switches must have multiple FETs per switching path and require one control line per path. Other disadvantages include low ESD tolerance (typically 250 V to 500 V human-body model (HBM)) and the need for additional decoding and dc-blocking circuitry.

RF CMOS has recently made inroads into front-end switching (Figure 1c). Traditionally, it has been used only for low-voltage applications, but new process technologies are moving it beyond standard CMOS to deliver RF CMOS switches that satisfy GSM and WCDMA requirements. Today's RF CMOS processes can be divided into two main categories, bulk CMOS and silicon-on-insulator (SOI). Bulk CMOS is built on a silicon substrate that is not a fully insulating material, which makes it inherently limited for producing high-power, highly linear switches. However, SOI processes can place multiple FETs in a series to handle these high voltages. A special subset of SOI is silicon-on-sapphire, known as UltraCMOS.

SP6T and SP7T mobile handset switches (Figure 2) have been implemented in UltraCMOS, a process based on standard RF CMOS where devices are developed directly on top of sapphire. This technology offers the traditional benefits of CMOS — ease of integration, low cost, low power, repeatability and scalability — and offers performance benefits over III-V semiconductor compounds, such as GaAs.

The most notable advantage of UltraCMOS is the insulating sapphire substrate, which essentially eliminates the parasitic drain capacitance that is evident in bulk silicon. For switches, this is a key factor because it allows the design of multiple RF components on a single die with minimal crosstalk. UltraCMOS differs from other SOI technologies as well. In most SOI technologies, a thin layer of insulating dielectric material is required between the MOSFET device and the silicon layer. While this approach reduces the effects of the parasitic capacitances and leakage currents, it significantly limits device performance.

UltraCMOS, on the other hand, uses a highly insulating substrate that provides better isolation between circuit components, making it especially well suited for use in triple- and quad-band GSM systems. And, because it uses a thin 50 Å to 1000 Å layer of silicon on top of the sapphire, UltraCMOS eliminates the need for body diodes and offers inherent dielectric isolation between the transistors.

In fact, switches manufactured in UltraCMOS are achieving notable performance benefits. Developed in a series-shunt configuration to further improve insertion loss and isolation (Figure 3), UltraCMOS RF switches have an integrated decoder so they do not require the additional control signals that GaAs switches do. In addition, blocking capacitors are eliminated because the switches integrate a negative voltage generator to turn the FETs off. The shunt devices are directly connected to ground (providing a path for ESD current) and low isolated-state impedance makes the switches immune to load pulling on isolated ports. Figure 2 shows a switch with integrated ESD protection circuits on the digital control lines. (For this switch, HBM tolerance is 1500 V, and the antenna node tolerates 4000 V HBM.)

Another challenge in GSM switch design is satisfying the linearity requirement. The SP6T switch in Figure 3 handles +38.5 dBm output power at 0.1 dB compression and +41 dBm output power at 1 dB compression.

Performance characteristics can be further enhanced with the addition of HaRP technology, which was developed to improve harmonic performance and linearity in UltraCMOS designs. Traditional switch technologies, such as PIN diode and GaAs pHEMT, provide only 6 dB of margin in harmonic performance. This lack of performance headroom usually translates into multiple design iterations to meet GSM specifications. By comparison, at an operating power of +35 dBm, the HaRP-enhanced UltraCMOS switches deliver 20 dB of margin (Figure 4). The second harmonic is intrinsically low in UltraCMOS technology because distortion is symmetric on positive and negative voltage swings. Good performance here is crucial, because the second harmonic of the GSM transmit band falls within the DCS receive band. In terms of linearity, switches built on HaRP-enhanced UltraCMOS have demonstrated third-order intercept (IP3) points greater than +70 dBm. This is important to meet the 3rd Generation Partnership Project (3GPP) standards body intermodulation specification for WCDMA handsets, which requires the switch to have an IP3 above +65 dBm.

While it meets the architecture and performance requirements of GSM/WCDMA handsets, UltraCMOS offers significant size and integration advantages. For instance, these switches can be flip-chip mounted to a low temperature co-fired ceramic (LTCC) substrate without underfill, eliminating the area previously required for wirebonding. Currently, wafer-level chip-scale packaging is in development to produce switches that can be handled like a standard surface-mount package.

Using UltraCMOS eliminates the decoder, blocking capacitors, and the diplexer that are required with other switch technologies. Combined with chip-scale packaging technology, it can dramatically reduce the size and thickness of ASMs. Inherent ESD tolerance and a monolithic CMOS interface simplify implementation and use. Finally, the high yield of UltraCMOS processes and scalability to additional switch throws provides a roadmap to even higher levels of integration for future generations of handsets.

Rodd Novak is vice president of marketing for Peregrine Semiconductor. He is responsible for the design and execution of the company's global product marketing strategy. He also directs the company's strategic business development activities. He can be reached at rnovak@psemi.com.

Based on standard CMOS processing, UltraCMOS is an example of leading-edge RF CMOS technology where devices are developed directly on top of a sapphire. The insulating, single-crystal alumina properties of sapphire provide UltraCMOS with interesting performance advantages. For instance, it maintains all of the positive attributes of bulk CMOS (including the low-power operation, manufacturability, repeatability, scaling properties, and IP block re-use), yet it delivers RF performance similar to GaAs.

Figure A demonstrates the difference between UltraCMOS and traditional bulk CMOS. In UltraCMOS, a layer of approximately 1000 Å of silicon is deposited on top of the sapphire. This provides for fully depleted devices with no body junctions — leaving cox as the only voltage variable capacitance and zero substrate leakage currents. As a result, UltraCMOS provides for faster devices, reduced CV^2f power loss, excel-lent linearity, high isolation, and no kink effect.

High-Q passives can also be manufactured in UltraCMOS. The transistors are dielectrically isolated to provide latch-up immunity and high isolation. With such a thin layer of silicon, the body terminal of the device is eliminated, making it a true three-terminal device. UltraCMOS is currently being manufactured on standard six-inch CMOS processing equipment, and fabrication on eight-inch lines has been demonstrated. Yields are comparable with other CMOS processes. By using UltraCMOS instead of bulk CMOS, RFIC designers can improve the linearity, isolation, insertion loss, electrostatic discharge (ESD) handling and power consumption of digital circuits, all while realizing the cost advantages of CMOS.

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