Question 2: Before we launch into specifics, can you first broadly describe your past and present development flow, and where you see the main pain points?

Warwick: For our customers the flow is generally something like:

1. Collect requirements, standards and an inventory of legacy and innovative algorithms and IP (internal and third party).

2. Validate executable specification at the functional/behavioral level.

3. Architectural exploration where issues like processor loading, need for hardware acceleration, and bus contention are resolved.

4. RFIC design with system-level verification possibly using “simulator-in-the-loop” and verification model extraction.

5. System-level verification with “hardware-in-the-loop.”

The biggest pain is in step 4. In particular, how best to reconcile RF circuit metrics like noise figure, network parameters, AM/AM and AM/PM conversion, memory effects, with system-level metrics like BER vs. signal to noise ratio (SNR).

Niehof: In the past we were designing single functional blocks/ICs (VCO, LNA, PA). Now the market is demanding complete system solutions, RF SoC (Bluetooth, WLAN and UWB). This implies changes in the design methodology and tooling. We can no longer design in the traditional analog/mixed signal and RF silos.

Arkiszewski: I can tell you what works well today. Appropriate behavioral modeling of sub-blocks for use in higher-level (more abstract) simulations. Verification of behavioral models against transistor level blocks, and effective simulation/verification planning to ensure adequate coverage of functional operation and performance of the (sub)system(s). Various levels of co-simulation: AMS/Verilog-D, A; ADS Ptolemy/Verilog-D, A, MATLAB, and transistor FastSpice for functional verification.

Kanaglekar: This is the flow we have seen most of our communications system design customers follow: algorithm design/exploration, system architecture exploration/design that specifies which parts will be done in A/RF, digital, DSP, hardware and software. At this point, the RF design team takes the RF specs and goes through an RF system and subsystem design, followed by transistor-level design of each block in the subsystem. The RF portion then goes through a post-layout verification. The baseband design team takes the baseband specs and goes through a similar flow of baseband algorithm and hardware/software design. The most challenging part is then to combine the A/RF section and the baseband section to verify the overall RF/mixed-signal system with simulations as well as with test and measurement instruments. There are two main pain points in this flow: verification of RF blocks in the top-level system environment and verification of the overall A/RF/mixed-signal system at the end.

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