Question 3: We hear a lot about the RF simulation bottleneck, what is that? Can you give some examples?

Warwick: The actual RF signal is the combination of a medium-frequency envelope modulation imposed on a high-frequency carrier wave. To simulate all the effects of this combination, you'd have to do a transient simulation with time steps much smaller than the carrier period: a costly proposition. Most of the information is in the envelope, which varies much more slowly, allowing you to chew up much more simulated time with every computation cycle. But it requires careful surgery to extract the envelope from the carrier without losing fidelity.

Hartung: A key bottleneck to enable RF/baseband co-design is the presence of the RF carrier signal at several GHz in the RF front-end. To simulate the bit error rate (BER) or package error rate (PER) of a complete telecom link at transistor-level running thousands of cycles of the modulated signal is at a minimum expensive and is often impractical.

Niehof: How to include the RF part in the complete system simulation. For most of the system it is a matter of timing; time-domain simulations, whereas the RF blocks are designed and simulated in the frequency domain. Due to large (several orders in magnitude) differences in signal frequency, simulating an RF block is already difficult by itself. EM simulation tools, for example, output their calculation results in S-parameters. This makes it virtually impossible to include RF layout details in a time-domain simulation with other parts of the system.

Arkiszewski: Here I can talk about what is missing today. Vendor design kits often do not work well with tools “out of the box.” Problems caused by interactions between circuits are a larger issue now than circuit-level behavior. In particular, EM and substrate coupling effects are difficult to model effectively with today's tools. The bottlenecks could be greatly reduced if automated methods to extract transistor-level simulated performance into the higher-level simulations were improved. Then transistor model to behavioral model equivalence could be established.

In some cases, behavioral models are manually updated with transistor-level parameters. Additionally, as various tools exist within the RFIC designer's and system designer's toolboxes, behavior model portability is key. Re-developing models for different tools, can waste precious time in the development cycle. Further improvements in power amplifier (PA) non-linear modeling would help as well. In some cases, behavioral models are only accurate when updated with characterization results.

Kanaglekar: The two primary bottlenecks in RF simulations are a result of 1) shrinking geometries giving rise to an exponential increase in the number of devices in a circuit; and 2) increased complexity of signals in today's wireless communications standards that these circuits are subject to. For example, to accurately represent a signal consisting of two carrier signals — say 2.4 GHz and 2.41 GHz — that are only 10 MHz apart, a Spice-like time-domain simulator needs to use enough time points to sample the carrier signals, and at the same time, perform a long-enough simulation to accurately sample the 10 MHz signal. Harmonic balance simulators get around this problem by performing the simulation in frequency domain. But for complex modulated signals or digital waveforms requiring many harmonics, even harmonic balance simulators can run into capacity problems. That's where envelope simulation techniques come in the picture. An envelope simulator samples the modulation waveform in time domain and simulates the carrier(s) in frequency domain. Another common technique to get around the capacity limitation is to extract behavioral models for sub-blocks in the circuit and to simulate the overall subsystem by combining these behavioral blocks.

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