How to best marry time-domain system-level verification with frequency-domain RF circuit simulations Sep 1, 2006 12:00 PM
By Ashok Bindra, Editorial Director
This article is a discussion based on a panel presented at the IEEE MTT-S International Microwave Symposium in San Francisco, Calif. RF Design posed six questions to six panelists on the topic
of system-level verification of RF circuits and compiled their responses. The panel discusses the pros and cons of various methods that enable system-level verification of RF circuits.
Kanaglekar: The discussion in this panel session has focused primarily on the technical aspects of how to marry the time-domain system-level simulations with frequency-domain RF circuit-level simulations. However, there is another important aspect of this issue, the language gap. Hence, we should pay attention to “the “language gap” between the system architects/designers and RF circuit designers. RF circuit designers typically are not used to performance specs such as CCDF, BER, etc. When verifying their RF block in the system environment, the complexity of the system-level test harness should be hidden from them. Ideally, an RF circuit designer should be able to simply “drop” his/her design in a pre-configured test bench for a specific wireless standard and push a button to check whether the RF block passes the system-level specs. In other words, the overall verification flow in a given design environment and its usability are as important as the underlying simulation and modeling technologies.
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