Using 130 nm silicon germanium (SiGe) process technology, wafer scale integrated radio and antenna array developer TiaLinx, Inc., based in Newport Beach, Calif., has developed ultrahigh-speed analog-to-digital converter (ADC), multiplexer (Mux) and de-multiplexer (De-mux) cores for design of ultrahigh speed data acquisition system, UWB transceivers, optical transceivers, advanced coding systems and test & measurement.

"The core designs were developed with the support of DARPA/Army's contract number W31P4Q-06-C0380 for advanced wafer scale based radar systems," commented Fred Mohamadi, Founder and CEO of TiaLinx. "Taking advantage of greater than 200 GHz cutoff frequency offered in a SiGe process and advanced design architecture of TiaLinx, the Cheetah core set is revolutionizing multi- discipline DoD and commercial projects and positioning the company to be a leader in addressing applications related to precision target detection, test and instrumentation, and optical networking markets."

The core set includes an ultrahigh-speed flash ADC core (Figure 1) that addresses 50 gigasamples per second (Gsps) sampling. The ADC core interfaces to an ultrahigh-speed de-multiplexer core to address distributed signal processors. Unique features of the ADC core is its design to address spurious free dynamic range (SFDR) of greater than 27 dBc with 4 bit resolution and a power consumption of less than 10 W. It is designed to handle 25 GHz signal sampling and a clocking rate of 60 GHz. A companion Mux core has also been implemented to address the entire integrated core set's testability.

The Mux and De-Mux cores (Figure 2) have capability of greater than 100 Gbps link routing and have programmable, reconfigurable number of I/Os. On-board pseudo random bit sequence (PRBS) engines for in-situ testability are being designed for next generation core set. Testing and measurement of ultrahigh-speed digital I/Os are often met with bottlenecks arising from lack of availability of equipment being capable of handling the upper bands of millimeter waves to which the data is fed from ADC converters. This ultrahigh-speed demultiplexer core addresses gearing down to 128 lower speed I/Os at >100 Gbps data rate, explained Mohamadi. This unique core has been designed to interface to an ultrahigh-speed ADC of distributed signal processors with advanced coding systems for wireless applications, added Mohamadi. The core also addresses the de-mux function of Gbps and terra-bit-per-second (Tbps) of optical transceivers, switch and router backplanes, respectively, continued Mohamadi. Both, Mux and De-mux cores consume 4 W at 60 GHz clock.

While the company has seen the silicon, the cores are only partially tested. Full characterization is expected by the end of the second quarter. Consequently, TiaLinx will be ready for select sampling by the end of the second quarter, according to Mohamadi.

www.tialinx.com

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