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By rotating layers, a higher hole mobility is poised to improve future generation CMOS technology Jun 25, 2008 2:51 PM
Toshiba Corporation has announced that, together with IBM Corporation, they have developed a higher-performance CMOS FET for advanced system LSI. In their new methodology, by rotating the plane of standard (100) silicon wafers by 45 degrees and thinning the DSB layer of this substrate, they have diminished ring oscillator delay by as much as 30%, when compared with standard (100) wafers. The achievement was announced on June 19 at the VLSI Symposia 2008, in Honolulu, Hawaii. Though high performance, low power and scalability have won CMOS technology a central place in semiconductor technology, its ability for further advances has been threatened as CMOS scaling approaches fundamental physical limits that not only inhibit further advances in transistor performance but also migration to finer processing geometries. As a consequence, the semiconductor industry has been seeking new ways to overcome these challenges. Approaches have included adoption of new materials such as High-K, metal gate and new structures. Yet another way to improve performance is to increase the mobility of electron, or holes, through device channels. Direct silicon bonding (DSB) wafers is a bulk CMOS hybrid type wafer that bonds (100) and (110) substrates. It is a recognized candidate for advancing this approach. CMOS is comprised of two types of transistors: positively charged field effect transistors (P-FETs) and negatively charged FETs (N-FETs). In the case of P-FETs, hole mobility is known to achieve a higher performance on substrates with (110) surface-orientation than on substrates with (100) surface-orientation. However, for N-FETs, electric charge mobility deteriorates on a substrate with (110) surface-orientation, compared to mobility on a substrate (100) surface-orientation. Toshiba and IBM achieved the newly announced performance using new hybrid-orientation technology fabricated on a hybrid substrate with different crystal orientations to achieve significant P-FET performance improvement without degradating N-FET performance. Toshiba is studying various technologies for future advanced devices, and believes that its new technology is a step forward to more powerful practical devices.
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