Front-end components are useful in a wide range of communications systems, especially when multiple functions can be integrated into a single S-band transmit/receive (T/R) chip. As part of a class project at Johns Hopkins University, students in the JHU MMIC Design course, with assistance from the GaAs MMIC foundry at TriQuint Semiconductor, designed and fabricated an S-band T/R circuit designed for low-power battery operation at S-band. The transmit section includes a binary-phase-shift-keying (BPSK) modulator, amplifier, and T/R switch while the receive section featured a low-noise amplifier (LNA). The device was fabricated using a standard 0.5-ìm pseudomorphic-high-electron-mobility-transistor (pHEMT) GaAs process from TriQuint.

As part of the 2009 JHU MMIC Design class, students were asked to design a 2.4-GHz MMIC front end with low power consumption for operation from a battery supply at 2 to 6 V. Design support is typically available in the form of computer-aided-engineering (CAE) tools from Agilent Technologies and AWR Corp.

The S-band front end consists of the BPSK modulator, a medium-power amplifier, T/R switch, the LNA, and two differential driver circuits (Figure 1). To simplify input and output signals to the front-end MMIC, a circuit was designed to produce differential switch control signals from a single digital input. Both the BPSK modulator input and T/R switch input used this differential circuit to drive the enhancement-mode (E-mode) pHEMT switches. When the T/R switch is configured for transmit operation, a digital data stream is modulated on a carrier supplied at the RF input, amplified, and output via the antenna connection. For receive operation, the antenna connection becomes the input which is amplified by the LNA and supplied to the RF output connection.

A relatively small 4 x 15 ìm E-mode pHEMT device was used for the LNA and the medium-power amplifier as a compromise between performance, bandwidth, and DC power consumption. The current bias for the LNA was less than that of the medium-power amplifier to minimize noise figure while providing sufficient gain. A small current mirror bias was used to DC bias the two amplifiers so that they could tolerate a large supply range from 2 to 6 V with low current consumption.

Ideally, a lower voltage range of 2 to 3 V would minimize the overall DC consumption and maximize battery life. Each current mirror uses a 1 x 2 ìm depletion-mode (D-mode) pHEMT device as a current source of 0.4 to 0.5 mA which connects to a small E-mode pHEMT to set the gate voltage to a proportional, well-controlled current bias of the E-mode pHEMT in the amplifier. The E-mode pHEMT is 1 x 4 ìm in size to set the medium-power amplifier DC bias to about 7 mA, while a 1 x 12 ìm device was used to set the LNA DC bias to a lower 3 mA current. The DC bias for the entire MMIC is about 10 to 11 mA for modest 20 to 30 mW power consumption from a 2-to-3-V supply.

Broadband BPSK modulation is achieved by alternately switching a three-element lowpass filter and a highpass filter into the signal path, creating a broadband 180-deg. phase shift from the RF input to the medium-power amplifier. A design goal was to use positive voltages to control the switches, so E-mode pHEMTs were used as the switching devices.

Because it is important to limit the positive voltage driving the E-mode switches, a large resistor at the switch gates can serve this purpose. In this front-end design, a combination resistor divider and diode was used to limit the switch control voltages to the switches. Four 6 x 100 ìm E-mode pHEMTs are used in pairs to switch between the highpass and lowpass filter states to control the digital modulation. Figure 2 shows a schematic of the original BPSK modulator design.

Both amplifiers are based on a relatively small 4 x 15 ìm E-mode pHEMT device that was chosen as a compromise among performance, bandwidth, and DC power consumption. To achieve good low-noise performance, the current is limited to less than 3 mA using the current mirror bias circuit. The matching circuits were designed for stability, gain, return loss, and noise figure tradeoffs (see ref. 1). Figure 3 shows a schematic of the LNA design. Simulations performed on the LNA circuit predicted a respectable noise figure of 2 dB with good gain for the relatively narrowband amplifier.

Including the losses of the T.R switch, the LNA’s noise figure was predicted to be about 2.7 dB according to the simulations, with just over 13 dB small-signal gain (Fig. 4). Actual measurements on the fabricated MMIC were close to these predictions, with measured small-signal gain of about 12.5 dB overall and noise figure of 2.9 dB.

The medium-power amplifier is also based on the 4 x 15 ìm E-mode pHEMT device, chosen as a compromise between performance, bandwidth, and DC power consumption, with a goal for the amplifier of delivering 5 to 10 mW RF output power. To design an amplifier for power using pHEMT devices, the current is biased to about 7 mA using the current mirror bias circuit. The impedance matching was designed to reach a compromise in performance for stability, gain, return loss, output power, and power efficiency.

Figure 5 shows a schematic diagram of the medium-power amplifier circuit. According to CAE simulations, output power of +8 dBm was predicted, with reasonable gain and power-added efficiency (PAE) in the range of 36% to 38% (Table 1). When the losses of the T/R switch are included in the simulation, the predicted output power is about 5 mW (+7 dBm) with good gain and similar PAE performance to the earlier simulation. Due to a problem with the BPSK modulator driver/bias circuitry, the gain and overall performance of the transmitter section were less than expected, but improvements are possible by adding a small resistor connected to ground in the BPSK modulator circuit.

Since the medium power amplifier was not expected to produce more than 10 mW RF output power, the E-mode pHEMTs can be used for switch devices and will not compress at that signal power level. For greater power-handling capability, D-mode pHEMTs could be used, but a secondary goal is to use positive voltages to control the switches. This could be done with the negative D-mode pHEMTs, but requires capacitors and a positive voltage reference. These additional components only add to the circuit complexity and take up addition die area compared to implementing the design with lower-power E-mode pHEMTs. As with the other switches in the front-end MMIC, the positive voltage must be limited to the E-mode pHEMT switch devices, and this can be accomplished by means of a large resistor at the gates of the switch devices.

Figure 6 shows a schematic diagram of the T/R switch. It is a single-pole, double-throw (SPDT) arrangement with a series 6 x 100 ìm E-mode pHEMT followed by a shunt 6 x 50 ìm E-mode pHEMT in the transmit and receive paths. The switch provides high isolation with fast switching speeds.
The overall front-end layout was intended for a 54 x 54 mil die, but since there was a 54 x 84 mil die available on the JHU class tile, the RF front end occupies the bottom two thirds of the layout in Fig. 7. A separate test circuit fills the top third of the design, so the actual layout could easily fit a 54 x 54 mil die. The (bidirectional RF) antenna connection is on the left adjacent to the T/R switch. From the right, the BPSK modulator connects to the medium-power amplifier in the left-middle side of Fig 7. The LNA can be seen at the bottom with an output on the far right-hand side of the photograph. The front-end MMIC is designed for a supply voltage of 2 to 6V, but was actually intended to run on a supply voltage of 2 to 3 V for low DC battery powered operation. Digital inputs for the T/R switch and BPSK modulator are fed to two differential switch driver circuits to generate the complementary switch control voltages. The front-end IC design was tested with a wafer probe at the die level and also as a packaged part in a test fixture.

Testing was initially performed in March of 2010 using the probe station at JHU’s Dorsey Center. Figure 8 shows an S-parameter plot of the LNA with the T/R switch set to receive (solid lines) and in the isolated state (dotted lines). The results agreed well with the original simulations; the DC bias of the LNA was 3 mA, as expected. Figure 9 shows the transmit S-parameters with the T/R switch set to transmit; it also shows both states of the BPSK modulator. The gain was lower than expected, although the DC bias was at 7 mA as expected.

Additional measurements and simulations uncovered a slight problem resulting from simulating the blocks as individual elements but not simulating the overall project. A simple 5-kÙ resistor to ground was needed between the BPSK modulator and the medium-power amplifier to set a 0-V reference for the pHEMT switches. Figure 10 shows the addition of the DC ground reference, which is needed when the BPSK modulator is connected to a DC blocking capacitor. In the original BPSK modulator simulation, the 0V DC reference was supplied by the 50-Ù RF output port, but resimulating the circuit with a DC blocking capacitor before the 50-Ù RF output port shows the problem of having a switch with a floating ground. Figure 11 shows the expected performance of the BPSK modulator, power amplifier, and T/R switch with the added resistor “fix.”

Additional measurements of the LNA with a noise-figure meter showed good gain and respectable noise figure after adding in the T/R switch losses in order to match the conditions of the earlier simulations. S-parameter and noise-figure measurements were made from 2 to 5 V, showing a robust DC bias from the current mirror approach with little change in performance. Figure 12 shows the measured gain and noise figure at supply voltages from 2 to 5 V, with about 10 mA total current consumption for the entire circuit.
Testing of a packaged part was performed in April and again in September of 2010. Performance measurements were made of the packaged RF front end, but since the BPSK modulator had the DC reference problem, only the LNA performance is shown. The amplifier’s output 1-dB compression point and efficiency are reasonably good for the low 3-mA, 3-V bias (Table 2). Figure 13 shows a photograph of the GaAs MMIC die wire bonded into a 4 x 4 mm QFN package for board-level testing. If there is room on a future JHU MMIC Design class tile, the circuit should be re-fabricated with the “fix” to test the transmit portion of the design.

In short, an S-band RF transmit/receive MMIC with low DC power consumption was designed, fabricated, and tested using the 0.5-ìm TQPED pHEMT GaAs process from TriQuint Semiconductor. The design consumes about 10 mA current from a single voltage supply of 2 to 6 V, preferably below 3 V to minimize DC power consumption. In the rush to fill the empty space available on the design tile that is sent to the GaAs foundry for fabrication, the original circuits were simulated separately. A slight glitch occurred in the transmit path which requires the addition of a single large resistor to provide a DC bias reference for the pHEMT switches in the modulator circuit.

Acknowledgments

The author would like to thank all those who have supported the MMIC Design Course at JHU, particularly Craig Moore, his former co-teacher of the course, and the staff at TriQuint Semiconductor for fabricating designs for the students in this course since 1989.

References

1. John Penn, “Design A MMIC LNA With GaAs PHEMTs,” Microwaves & RF, November 2006, pp. 68.
2. John Penn, “Design MMICs on a Budget,” Microwaves & RF, April 2010, pp. 68.

JOHN PENN, Professor, Johns Hopkins University EP, Baltimore, MD; Team Lead, RFIC Design, Army Research Laboratory; (301) 394-0423, FAX: (301) 394-1700, e-mail: profpenn@gmail.com/john.penn@us.army.mil.