More digital signal processing and less analog circuitry is the formula for reducing power consumption in complex communications ICs, according to Teresa Meng, Stanford University professor and founder/CEO of Atheros Communications. Meng discussed the necessity of moving away from pure analog circuit functions in her keynote address, “Digitally Assisted Analog Circuit Design for Communication SoCs” at the recent IEEE MTT-S International Microwave Symposium.

In beginning her talk, Meng noted that there are many innovations and new ideas in communications signal processing today. As examples, she cited WCDMA, DFE, OFDM, antenna beam forming, and MIMO. But the criteria that make an algorithm appropriate for implementation are rapidly changing because the ability to perform digital computation is improving exponentially thanks to advances in CMOS process technology. However, the ability to implement complex analog circuit functions is not keeping pace. In noting this discrepancy, she posed the question of whether the ability to implement these functions is actually “degrading linearly.”

With these ideas in mind, Meng observed that “power dissipation has become one of the main showstoppers.” With modern communications ICs performing hundreds of GOPS per device, the question becomes how to perform these operations “at the lowest energy and the smallest [silicon] area” per device. Meng noted that with direct mapped hardwired functions, digital signal processing can perform 1000 MOPS/mW, while also achieving 1000 MOPS/mm2 of silicon. This efficiency contrasts with what can be achieved with an embedded FPGA (10 to 100 MOPS/mW) or a general-purpose DSP (0.5 to 5 MIPS/mW and 10 MIPS/mm2 of silicon).

However, the discrepancies in energy efficiency and silicon area efficiency that really matter are the discrepancies between analog and digital circuit performance. As an example of the silicon inefficiency of analog functions, Meng illustrated graphically how a 10-pF linear capacitor occupies 0.01 mm2 of silicon, which is equivalent to the space required by 2000 logic gates implemented in 0.13 µm CMOS. In contrast, an 8080 microprocessor core requires a little over 1000 gates. This discrepancy only gets more pronounced at finer process geometries. Similarly, Meng showed graphically how the energy consumed by state-of-the-art analog-to-digital converters (6 to 16 bits) equals the power consumption of hundreds of thousands of logic gates.

Meng conceded that the superiority of digital signal processing (in terms of silicon area and power dissipation) over analog is not a new concept. However, the gap between analog and digital technologies has widened because of advancements in the last ten years. This condition requires a change in approach to system-on-a-chip (SoC) design. According to Meng, the current paradigm in SoC design is “let’s use some logic gates to correct and calibrate analog circuits.” In the future, designers will need to ask, “How many analog transistors do we really need?” said Meng.

Although one key analog circuit design challenge—thermal noise—is fundamental, the challenge of distortion is not. Although the traditional approach to reducing distortion in amplifier design has been to apply high-gain feedback, doing so imposes penalties with respect to noise, dynamic range, speed, and power consumption when compared with an open-loop amplifier. However, Meng observed that it’s possible to design an amplifier to operate open loop and then use digital signal processing to linearize the amplifier’s output. By aggressively applying logic gates to “assist” analog functions such as ADCs and power amplifiers, it becomes possible to lower their power dissipation, according to Meng.