Combining its patented DSPLL technology with advanced 0.13 micron CMOS process, mixed-signal supplier Silicon Laboratories Inc. has entered the frequency control market with the launch of Si530 and Si550 families of crystal oscillators (XOs) and voltage-controlled crystal oscillators (VCXOs) for applications up to 1.4 GHz. The supplier claims that high reliability, high performance and short lead times offered by these oscillators are unmatched. Plus, according to the maker, these product families include the industry’s first quad frequency XO and VCXO devices. Target applications for these XOs and VCXOs include networking equipment, base stations, test and measurement equipment, storage area networks and video systems.

For both these families, the frequency range is from 10 MHz to 1.4 GHz with less than 0.3 ps RMS jitter. In addition, they offer significantly improved control voltage linearity and a wide selection of voltage gain and pull range options for greater design flexibility.

“Today, high-frequency, low-jitter oscillators are based on complex resonator technology that forces system manufacturers to endure long, unpredictable lead times and incur significant costs in qualifying and monitoring the reliability of these devices,” said Brad Fluke, vice president of Silicon Laboratories. “We are excited about applying our proven DSPLL technology to the long-standing problems associated with the high-frequency oscillator market while also introducing new levels of functionality.”

With optimized DSPLL technology, the developer is able to move frequency control and tuning from a complex resonator to a single CMOS IC, enabling the Si530 and Si550 families to deliver total frequency stability over time and temperature that is more than two times better than traditional high-frequency, low-jitter oscillators. DSPLL-based frequency tuning also enables up to a tenfold improvement in initial frequency accuracy when compared to designs based on traditional high-frequency SAW or crystal resonators, claims Silicon Labs.

"Silicon Laboratories' market-leading jitter performance challenged our best jitter measurement test system," said Amir Aghdaei, vice president of Agilent's Worldwide System Solutions Division. "We developed the JS-500 with very low intrinsic noise, great clock rate flexibility and true continuous peak-to-peak measurements specifically to help Silicon Laboratories verify their DSPLL-based products’ unmatched jitter performance metrics."

A new class of XO and VCXO devices, the Si530 and Si550 families leverage the frequency synthesis capability of a mixed-signal IC to eliminate complex materials processing steps required to frequency tune traditional SAW and crystal-based implementations. This simplifies the manufacturing process and significantly reduces traditional lead-times from eight weeks to only one week, said the manufacturer.

"Traditionally, PLL technology has not met the jitter and phase noise requirements for clocking networking and telecommunications applications," said Scott Smyser, director and principal analyst of iSuppli Corp. "A high performance, low-noise PLL brings increased flexibility, performance and reliability to designers that was not previously available from high frequency oscillator technology."

The Si530 and Si550 devices are available in an industry standard, RoHS-compliant, 7 mm x 5 mm surface mount package with support of all common output formats: PECL, LVDS, CMOS and CML. The Si530 and Si550 are sampling now with production scheduled for the fourth quarter.

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