Implementing multi-mode, multi-band wireless connectivity within the size, weight, cost and power consumption limitations of consumer products will require the challenging RF circuits to be integrated into increasingly complex nanoscale silicon chips. To address those issues, Philips Electronics, austriamicrosystems, MAGWEL, IMEC and the universities of Lisbon, Bucharest and Delft have joined forces in the European Union (EU) Information Society Technologies (IST) 6th Framework Program called CHAMELEON-RF project. This project is targeted at producing better tools for designing the complex nanoscale silicon chips at the heart of next-generation wireless communication products. By allowing the RF circuits needed in these products to be efficiently and reliably integrated into low-cost silicon chips, these design tools will help to ensure the timely introduction of ever-more advanced communications products that keep consumers connected wherever they are.

“The objective of the CHAMELEON-RF project is to provide chip designers with the electronic design automation (EDA) tools they need in order to achieve right-first-time RF designs,” said Wil Schilders, chairman of the CHAMELEON-RF consortium. “To do that we aim to create computer models that will allow silicon-accurate simulation of complete RF circuit blocks rather than single components.”

The group will develop simulation models that accurately predict the behavior of RF silicon integrated circuits at frequencies up to 60 GHz. It is considered necessary to enable next-generation, high data-rate wireless connectivity systems. These models will take into account the fundamental physical principles of the electrical current flow in circuits and devices and the electromagnetic fields they generate, as well as the electromagnetic interaction between these fields and the circuit components. They will also take into account the effect of process variations in the semiconductor processes used to fabricate the chips. The results will be built into simulation models that will run within the computational constraints of typical EDA workstations, enabling them to be incorporated into commercial EDA tools.

The CHAMELEON-RF project is funded under the European Union IST) 6th Framework Program and will last for a period of two and a half years. First results are expected around the middle of 2006.

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