While 2G cellular services such as GSM and CDMA are common, the rising demand for data and multimedia services is forcing service providers to offer 2.5G and 3G systems like EDGE/GPRS and UMTS/CDMA2000. Thus, the demand for multimedia functionality in feature-rich handsets is rising at a much faster rate. To support these enhanced functions in handsets, RF cellular ICs must provide small-form-factor low-power solutions, while meeting stringent system-level requirements. This week’s International Solid-State Circuits Conference (ISSCC) in San Francisco, Calif. provides a good snapshot of recent advances in cellular RFICs, ranging from power amplifiers to integrated transceivers. Several papers in Session 17 indicate that continued scaling of silicon can offer higher levels of integration with enhanced performance and reduced overall cost.

For instance, in paper 17.1, the researchers from Texas Instruments’ Bangalore, India center present a single SoC GPS receiver chip that integrates both the baseband and RF functionalities in an advanced 90-nm CMOS technology. Similarly, based on 0.23 µm LDMOS technology, a high-power GSM amplifier with 36 dBm output and 54 percent power-added efficiency (PAE) is given in paper 17.2 by Renesas Technology researchers in Takasaki, Japan. And Katholieke University in Leuven, Belgium (17.3) features a 0.18 µm polar-modulated CMOS GSM/EDGE power amplifier that can deliver 23.8 dBm with 22 percent PAE. A unique loop bandwidth-calibration technique for a fractional-N synthesizer is showcased in a joint paper by Hitachi and Renesas Technology (17.4). The calibration technique achieves better than 2° RMS phase error.

TI’s researchers based in Dallas, Texas, demonstrate an all-digital GSM/EDGE transmitter in an advanced 90 nm CMOS technology in paper 17.5. This 1.2 V 42 mA polar transmitter consists of a digitally controlled oscillator with digital amplitude modulation. It meets the EDGE spectral mask with an EVM of 3.5 percent. This paper also demonstrates the viability of scaling RF circuits in 90 nm CMOS technology. Furthermore, a fully integrated GSM/GPRS transceiver in a 0.18 µm CMOS technology is presented in 17.6 by Berkana Wireless, Campbell, Calif. This quad-band transceiver features a low-IF topology with no external SAW filter. A fifth–order continuous-time GmC filter with in-situ calibration, to achieve 2 percent tuning accuracy, is described in a companion paper (17.8).

Two direct-conversion receiver presentations round out this session. A 0.18 µm micron CMOS direct-conversion UTMS downconverter is presented in paper 17.7. The downconverter uses an LC filter to achieve a high IIP2 of 78dBm. A fully integrated direct-conversion CDMA receiver in 0.25 µm CMOS is described in paper 17.9. This receiver has a linearized LNA that enables a high IIP2 of 75dBm.

RSS    Save to Del.icio.us  Digg This