At Tessera's 2nd Annual Technology Symposium held last week in San Jose, several key executives and technologists from companies including Amkor, Gartner Dataquest, Intel, Nokia and Tessera convened to discuss the benefits and increased market adoption of system-in-package (SiP) technologies. Fueled in large part by the growing convergence of communications, computing and consumer electronics, the use of SiP as a design methodology provides distinct performance, cost and size advantages; however, the symposium also revealed several challenges still hindering mass-market SiP adoption.

The event was held on Tuesday, July 13 at the Hyatt Sainte Claire Hotel in downtown San Jose and was sponsored by Tessera Technologies, Inc., a technology developer and services provider for semiconductor chip-scale and multichip packages (CSPs and MCPs).

Kicking off the 2004 event was a keynote address on lowering the risk of SiP implementation from David Tuckerman, Tessera's chief technical officer. Tuckerman highlighted several SiP benefits, including reduced product development cycles and costs, increased flexibility for product upgrades and the ability to stack heterogeneous technologies (i.e. memory + logic) to minimize footprint and accelerate product miniaturization. Tuckerman also called for advancements in computer-aided design (CAD) and thermal modeling tools to better analyze multidie interconnections in 3D stacking configurations, as well as improved supply chain cooperation to address the known good die (KGD) and business complexities arising with greater system integration. Despite these challenges, Tuckerman noted the industry has made significant improvements in assembly yields and processes, and in the integration of passive components, all of which contribute to lowering the risk of SiP implementations.

Commenting on market trends, applications and analysis for multiple-die packaging was Jim Walker, vice president of research at Gartner Dataquest. Walker discussed key application areas for SiP technology, with cellular phones, WLAN, telecommunications equipment and memory cards among the biggest market drivers. He also presented market data showing that 5.7 billion SiP units--which includes a broad set of package types, such as FCIPs, MCMs and FBGAs--are expected to ship in 2004, with that number estimated to grow to 10 billion units in 2006/2007. The consumer market is among the largest SiP growth segments, expanding from 26 percent of the market in 2002 to 31 percent in 2003.

In the area of stacked-die and SiP applications, the symposium featured a presentation from Steve Greathouse, non-CPU pathfinding program manager at Intel. Greathouse discussed convergence in the consumer market as leading the demand for SiP technology, with increased functionality and performance in PDAs and other mobile communication devices a key driver for SiP adoption. He then discussed the growing need for advancements in wafer thinning technology as the industry approaches integration levels of 4+ die per package.

Echoing the theme of SiP market expansion was Mike Steidl, senior vice president of advanced product development at Amkor Technology. In his presentation, Steidl discussed the growing market for SiP technology in portable applications where increased functionality, improved battery life and seamless wireless connectivity are paramount. According to Steidl, having multiple packaging capabilities--such as wire bond, flip chip, die stacking and package stacking--combined with the ability to integrate them differently based on application specific needs--are key success factors for SiP vendors.

In a presentation highlighting the advantages and economics of stacking memory devices, Arthur Sainio, senior strategic marketing manager at SMART Modular, pointed toward stacked packages as one of the most cost-effective means of achieving increased memory densities in blade servers and other high-performance computing applications. He also predicted increased demand for package stacking technologies as DDR2 memory begins reaching higher volume production next year.

Speaking on the topic of achieving reliable lead-free (non-Pb) electronics in the consumer market was Viswanadham Puligandla, principal scientist, Nokia research center. Puligandla shared his research on the effects of thermal and mechanical stress testing required by consumer electronics in lead-free packaging. He explained that lead-free interconnections are complex in structure and morphology, and further analysis needs to be done on the effects of multimetal interconnects to solve problems such as tin whiskers, which can be detrimental to overall system reliability and performance.

Industry analyst Jan Vardaman, president of TechSearch International, examined the changing requirements of package substrates in SiP implementations. As SiP technology continues to evolve, substrate performance levels are becoming increasingly important, and the need for high-density substrates is growing rapidly. Surprisingly, Vardaman pointed out that industry demand for wire-bond substrates is currently exceeding supply, causing prices to rise.

Providing insight on the role of SiP in medical applications was Larry Czapla, senior vice president of the medical business group at PEMSTAR Medical. According to Czapla, the medical electronics market is moving in a direction of miniaturization and integration to create less intrusive, more reliable and higher performing patient care systems. The medical industry is beginning to look more closely at component-level packaging, specifically SiP, as a cost-effective and fast time-to-market solution to address miniaturization requirements. Examples of next-generation medical applications that can benefit from SiP technology include implantable hearing devices, non-intrusive imaging systems and implantable diagnostic equipment that can monitor and treat patient conditions.

Craig Mitchell, vice president of marketing at Tessera, presented an innovative approach to system design. Known as system-level integration and miniaturization (SLIM), this new architectural discipline calls for the design of electronics to be optimized for miniaturization from the outset of product design. SLIM-designed systems take full advantage of the leading packaging and interconnect technologies available in the market today and have been successfully applied to achieve dramatic miniaturization results, such as the integration of a microprocessor, FPGA, EPROM and DRAM in a single system the size of a dime.

Providing closing comments at the symposium was Gene Selven, publisher of ChipScale Review magazine, the media sponsor for this event. Selven touched on the trend of growing collaboration and industry cohesion between the front-end and back-end semiconductor manufacturing segments.

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