To enable fast and accurate characterization of high-speed computer interfaces, Agilent Technologies Inc. has released the J-BERT N4903A 7 Gbps and 12.5 Gbps pattern generators with complete jitter injection capabilities. Design and test engineers can now quickly and accurately stimulate serial high-speed ports with all types of jitter, enabling higher quality characterization of device performance, said Michael Metzger, product manager for Agilent’s HSDT productline. Providing an upgrade path to J-BERT, the N4903A pattern generator options can be used in combination with oscilloscopes, built-in error detectors or other analyzers. It allows the user to add complete J-BERT functionality over time with error detector, CDR and complete jitter tolerance test.

The next generation of multigigabit devices using technologies such as PCI Express, serial advanced technology attachment (SATA) and fully buffered dual inline memory module (DIMM) are being introduced in the computer industry. Engineers need simple, cost-efficient test solutions for characterization and conformance testing of these high-speed interfaces to meet time-to-market and cost objectives, noted Metzger.

Toward that goal, the new J-BERT N4903A 7 Gbps and 12.5 Gbps pattern generator options offer cost-efficient digital stimuli, enabling quick and accurate characterization and compliance test of high-speed serial interfaces. As a result, test engineers can use the J-BERT pattern generators to inject clean as well as worst-case jittered pattern and clock signals into the device under test. Analysis tools, such as oscilloscopes, built-in error ratios test, or other analyzers can be used to monitor the behavior of the device under test under ideal and worst-case conditions, according to Agilent.

The new pattern generators enable fast and accurate testing by simplifying worst-case jitter tolerance testing with built-in and calibrated jitter sources for random jitter (RJ), periodic jitter (PJ) and bounded uncorrelated jitter (BUJ). It allows eye closures of greater than 0.5 UI. Other key features include emulating intersymbol interference (ISI), testing robustness against differential-mode or single-mode noise, injecting commonly used spread spectrum clocks (SSC), and coverage of data rates between 150 Mbps and 7 Gbps or to 12.5 Gbps. To simplify instrument set-up for serial buses, it offers pattern sequencer and 32 Mbytes of pattern memory. Its sub-rate clock output can generate all types of clocks and data rate ratios. Furthermore, the pattern generators are designed to provide accurate results based on excellent signal performance with 20 ps transition times (20% - 80%) and 9 ps peak-peak jitter.

The new J-BERT N4903A pattern generator options are expected to be available by the end of this quarter. The expected price for the 7 Gbps option including the jitter sources for RJ, PJ and BUJ is $122,000, and $138,000 for the 12.5 Gbps option.