RF Design Magazine


Programmable delay line provides end-to-end accuracy
Oct 18, 2007 11:44 AM  By Mark Valentine, Technical Editor, Power Electronics Technology

Maxim Integrated Products’ DS1124 programmable delay line is the first to specify a delay tolerance from input to output, rather than to a reference output signal. Furthermore, both the analog delay path and the three-wire serial programming interface support the cascading of multiple devices, empowering designers with a virtually unlimited delay range in precision-delay applications. These capabilities make the IC ideal for applications requiring accurate open-loop control of an analog signal’s propagation delay. For example, they are well suited for delaying the horizontal sync (HSYNC) pulse in large-format LCD TVs, leading to higher-resolution displays (see the Figure).

According to Mike Overlaur, business manager for mixed-signal products at Maxim, the delay line IC uses a proprietary circuit architecture in which a series of delay cells are cross-connected into an oscillator. The output of the oscillator is then used to control a switched-capacitor network whose output behaves like a fixed resistor. The effective resistance of the output is then a linear function of the fundamental period of the oscillator.

Figure. The DS1124 programmable delay line can improve the resolution of large LCD displays.

To create a frequency reference, this adjustable output resistance can be compared to an ideal, zero-temperature-coefficient resistor by using an analog error amplifier. The error amplifier’s output is then used to adjust the common control signal fed to each of the delay cells connected to the oscillator. In this manner, the frequency of the oscillator can be changed up or down to make the resistance of the switched-capacitor network match that of the ideal resistor. This, in turn, maintains an accurate delay in each of the delay cells across the supply-voltage and temperature ranges of the device.

Leveraging the properties of monolithic integrated circuits, the chip also contains a group of free-standing delay cells that are well matched to the delay cells cross-connected to the oscillator. The free-standing delay cells provide the main analog signal path between the input and output of the device, and receive the same common control signal fed to the delay cells that are connected to the oscillator. Therefore, the delays in the free-standing cells are maintained with the same accuracy as the delays of the cells connected to the oscillator.

The analog input signal to be delayed by the IC is routed through the appropriate taps in the free-standing delay cell string using analog multiplexers. The multiplexers are selected according to the eight-bit delay code received by the serial digital interface to produce the correct delay value associated with the code.

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