Cadence Design Systems, Inc. has readied new capabilities that enable wireless chip designers and manufacturers to have better insight into the mixed-signal and RF challenges that significantly affect wireless design. Built on its Virtuoso custom design platform, the Cadence wireless offering combines new Cadence RF extraction technology, two new design flows tailored for wireless chip design, engineering services, silicon-proven IP, and integration with technology from Cadence partners Agilent, CoWare, Helic, and MathWorks. This offering provides access to a streamlined design process resulting in fewer re-spins and faster time to market.

Since parasitics are a major cause of failures in wireless designs, these issues are directly addressed by the RFIC flow featuring Assura RF, new Cadence technology that delivers complete extraction for RF design.

"The Virtuoso RFIC flow is a significant step forward and provides wireless designers with a substantial time-to-market advantage. The fact that Cadence uses real-world designs to streamline RF IC design front-to-back increases confidence and ensures faster implementation and adoption of new technology," said Werner Geppert, director, Analog Design Methodology, Infineon Technologies. "We look forward to continued collaboration with Cadence in this area."

Based on 802.11b wireless LAN design IP, the two new design flows included in the new Cadence wireless offering focus on front-to-back RF and analog/mixed signal design while at the same time bridging the gap between IC implementation and the entire system design. These flows enable simultaneous verification of the RF, analog and digital domains together and verification of the wireless IC design in the context of the system.

The flows integrate technology from Cadence partners to help streamline wireless design. Designers using Cadence Virtuoso AMS Designer can work with system design teams while leveraging the proven set of wireless standards libraries available for CoWare's SPW product. They also can move a design from the system level to the IC level more efficiently through the integration of MathWorks' MATLAB/Simulink with Virtuoso AMS Designer. Also included in the flows are Agilent's proven RF design and test technologies-RFDE, Momentum and Ptolemy-and Helic's VeloceRF, an advanced inductor design solution that minimizes errors associated with RFIC design cycles.

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