Leuven, Belgium based microelectronics research center IMEC has completed design and tape-out of a flexible-air-interface (FLAI) baseband platform for software-defined radio (SDR). According to the developer, its solution is designed to support upcoming generations of mobile devices featuring 802.11n (WiFi), 802.16e (mobile WiMAX), mobile TV and 3GPP-LTE communication standards. The system-on-a-chip (SoC) platform and its patented components with their programming environment will be licensed to industry for commercial product development as white-box intellectual property (IP), said the developer.

Implemented in 90 nm CMOS, the FLAI platform incorporates two IMEC-proprietary architecture for dynamically reconfigurable embedded systems (ADRES) baseband processors fully supported by a proprietary C-code compiler, three digital front-end tiles with a proprietary application-specific integrated processor (ASIP) to assure sync-detection, an ARM 9 processor, and optimized AMBA interconnect to link the SoC’s modules with on-chip memories. The IP blocks come with reference platform control software and reference firmware for IEEE802.11n, 802.16e and 3GPP-LTE, as well as integration support.

Thanks to a patented platform control and power management approach, the SoC consumes only a few mW in standby mode, yet is still capable of receiving an immediate burst from any supported wireless standard (reactive radio). When transmitting or receiving data bursts with multi-antenna encoding at more than 100 Mbps, platform peak power is only 300 mW, according to IMEC.

IMEC also expects to combine its FLAI platform and flexible radio front-end (SCALDIO) in order to demonstrate a fully operational SDR radio later this year. This platform achievement will be followed by a new generation of SDR research results, focusing on SDR and cognitive radio now under development, stated IMEC. This new generation also includes a unified application-specific processor architecture that can reduce the area cost of implementing multi-mode advanced forward error correction.

Key specs of the FLAI include 38 mm² die area, 4 power domains, 8 clocks, 270 I/O pins, and 6.7 Mbytes of memory. Plus, it operates at a speed of 25.6 GOPS.

Not fully characterized yet, the chip will be housed in a plastic BGA (26 x 26 balls) package.

www.imec.be

IMEC SDR Diagram

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