|
|||||||||||||||||||
|
|
High-density TDM switches set new standard For wired and wireless networking Jan 23, 2004 12:00 PM Ottawa, Canada -- Zarlink Semiconductor has launched a fully featured TDM/TSI switch family, setting a new performance standard for high-density switches designed into next-generation converged and wireless networking equipment. Zarlink developed its 32 K ZL 50073 TDM switch family to meet the exacting requirements of high-bandwidth, wired and wireless networking equipment such as media gateways, wireless base stations, and remote access concentrators that carry converged voice, data and multimedia services. Customers are also demanding higher-performance TDM devices to upgrade the Class 4/Class 5 Central Office switches that still dominate today's carrier networks. Zarlink's four-device ZL50073 family provides a flexible and cost-effective centralized switching approach for high-bandwidth voice and data equipment. The family's ZL50073 switch doubles the capabilities of competing high-density devices, offering 128 input and 128 output streams for interfacing to peripheral components and different data rates up to 64 Mbps. The ZL50073 family boosts the performance of high-bandwidth TDM equipment while also lowering board-level design cost and complexity. The devices include programmable data rate conversion circuitry, permitting them to directly transmit information between peripheral components without requiring intermediary FPGAs (field programmable gate arrays), glue logic, or other external circuitry that increases board complexity and cost. Zarlink's rate conversion technology provides flexible bandwidth allocation capability, allowing designers to select data rates on a per group of two-stream or four-stream basis. The ZL50073 TDM switching family achieves exceptional jitter tolerance, permitting the switches to be timed directly from the backplane's clock and frame pulses. This eliminates the need for intermediary chips such as CPLDs (complex programmable logic devices) and FPGAs. If reference switching or holdover functionality is required, high jitter tolerance means the designer can choose from a range of low-cost digital PLLs (phase-locked loops). The ZL50073 devices offer three clock inputs accepting selectable frequencies of 8-, 16-, 32- or 64 MHz. Other commercial high-density TDM devices provide only a 32 MHz clock input, severely limiting a designer's options when choosing a timing device.
|
|
|||||||
| Back to Top |