Renesas Technology and Matsushita Electric (Panasonic) have developed a technique that achieves stable operation with 45 nm process generation bulk CMOS for SRAM that can be embedded in SoC devices and microprocessors. Tests of an experimental chip with 512 Kbit SRAMs employing this technique have confirmed stable operation over –40 °C to 125 °C, and a larger operating voltage range margin with respect to process variations.

The experimental SRAM chip, produced using a 45 nm CMOS process, incorporated two different memory cell designs, one with a cell area of 0.327 µm² and another with a cell area of 0.245 µm².

The solution for a six-transistor type SRAM memory cell that Renesas Technology and Matsushita have developed has two elements. One is a read-assist circuit that performs automatic adjustment linked to V_TH variations. The other is a write-assist circuit that uses hierarchically structured power supply wiring.

The new read-assist circuit employs the resistance of passive elements in a compensation function that has a layout resembling that of the memory cell. Since memory cell variations and resistance value fluctuations are linked, the effects of V_TH variations are reduced.

The new write-assist circuit adds finer power supply lines (divided into eight) to the memory cell's column-unit power supply lines in a way that the isolation needed for the write operation is performed only where necessary. Also, it implements hierarchically structured power supply wiring. This reduces power supply line capacitance in critical areas, allowing the power supply line potential to be dropped to a low potential at high speed.

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