At this week’s Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC) in Anaheim, Calif., Silicon Laboratories Inc. displayed what it claims as the industry’s first jitter-attenuating clock multiplier IC that generates any output frequency from any input frequency with 0.3 picosecond jitter performance. The Si53xx any-rate precision clocks product family features nine devices leveraging the supplier’s proven DSPLL technology to offer a broad portfolio of reconfigurable, frequency-agile precision clock sources. The Si53xx any-rate capability addresses a wide range of high-performance applications including next-generation networking, telecommunications, wireless base stations, test and measurement, HDTV video and high-speed data acquisition.

According to Silicon Labs, the high-performance Si53xx is the first clock multiplier to generate any output frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from any input frequency between 2 kHz and 710 MHz. The ultra-low jitter generation of the Si53xx rivals traditional analog PLLs built discretely using expensive voltage-controlled crystal oscillators (VCXOs) or voltage-controlled SAW oscillators (VCSOs). The Si53xx family features an integrated loop filter with selectable bandwidths, allowing designers to change the loop bandwidth without changing components and enabling jitter performance optimization at the application level.

The Si53xx integrates a rich set of features on-chip, reducing the BOM while optimizing jitter performance. Plus, it includes an ultra-low phase noise, frequency-agile voltage-controlled oscillator (VCO), loop filter, phase detector, divider and buffers. Traditional PLL designs require discrete components, creating noise entry points between circuit elements. By eliminating the noise entry points, the Si53xx simplifies the task of achieving ultra-low jitter performance. Additionally, the Si53xx family supports up to four clock inputs and five differential clock outputs, eliminating the need for external muxes and clock distribution buffers traditionally used in complex timing subsystems of modern communications equipment.

Unlike traditional PLL implementations that only operate over a limited frequency range, the Si53xx family can be digitally reconfigured to operate over a broad range of frequencies, removing the need for multiple expensive VCXOs or VCSOs and easing design reuse. The Si53xx family also supports hitless switching to absorb phase differences between input clocks during a clock switchover.

The Si53xx family consists of four any-rate clock multipliers (Si5322, Si5325, Si5365 and Si5367) and five any-rate clock multipliers/jitter attenuators (Si5316, Si5323, Si5326, Si5366 and Si5368).