Silterra Malaysia and IMEC have signed an agreement for a joint development project (JDP) to create a foundry-compatible 90 nm CMOS process technology with the intention to further scale to 65 nm. A 110 nm derivative will be developed in parallel. This collaborative project is an extension of the JDP conducted earlier for 130 nm technology that is already in production at Silterra.

The technology will be ready for production by the second half of 2008 and will utilize a low-K inter-metal dielectric and the 193 nm patterning process. The smaller geometries will allow for smaller die sizes and faster transistors. The 90 nm process will have physical design rules and electrical characteristics that match mainstream technologies.