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Understanding ATE production test Nov 1, 2006 12:00 PM By Kyle Klatka With careful test strategy consideration, semiconductor companies can achieve product quality and cost aspirations for the UWB market.
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When introducing any product to market, a semiconductor company strives to deliver its customers the highest-quality solution so they continue to place orders. The introduction of ultrawideband (UWB) technology into high-volume production presents challenges beyond those typically associated with a product introduction. First, UWB's RF spectral characteristics present new test and measurement complexities compared to typical RF production tests for cellular transceiver or connectivity devices. Second, some industry observers anticipate rapid UWB market adoption, which could result in a steep time-to-volume ramp and ASP compression. These conditions set the stage for competing operational objectives. On one hand, there is a need to add capability and potentially cost, to a typical RF production test solution. On the other hand, companies are trying to reduce the cost to test each device. The test strategy for UWB devices, therefore, should include an automated test equipment (ATE) platform that offers engineers the flexibility to adjust fault coverage as needed and efficient multisite testing. ATE test and measurement challenges for UWB include frequency band coverage up to 10.6 GHz and a 512 MHz RF channel bandwidth. Depending on the chipset's feature set (e.g., onboard PCIe port), level of integration (e.g., single-chip solution), and electrical access (e.g., access between RF and baseband), the test plan might include basic per-pin testing such as continuity and current leakage, device-specific parametric measurements and RF tests. A typical test list for the RF transceiver block may include power/gain test;1 dB compression point; IP3; spurious emissions; gain flatness; noise figure and IQ imbalance. The RF test list and approach can vary depending on the level of fault coverage and performance validation desired, versus the cost to enable these tests. If built-in self-test (BIST) capabilities have been designed into the device-under-test (DUT), this contributes to the discussion. During the initial phase of the production ramp, the test list may include a more comprehensive list than shown above and appear similar to the characterization test list, including a full suite of modulated and continuous wave (CW) parametric tests. A characterization-centric test list typically offers increased device performance validation and manufacturing visibility. When polling operations managers responsible for the ramp of a UWB device or devices, three goals were consistent in their feedback — minimize cost, minimize cost and minimize cost. While the test list is likely to change as a result of product design and process stability, the ATE platform must be designed for multisite testing and enable high parallel efficiency to reduce the cost of testing each device. Parallel efficiency can be calculated with the following formula: The highest efficiency occurs when the total test time for a multisite program is the same as a single-site test time. While it is critical that the ATE platform offer instrument modules that align to the technical needs, the test program's parallel efficiency is more dependent on the overall architecture of the platform. For example, the underlying platform architecture needs to enable simultaneous instrument set up and settling, instead of sequentially incurring these tasks. Also necessary to increase parallel efficiency is the ability to perform any additional mathematical signal analysis and measurement computation in the background or while the instrumentation continues executing the measurement test list. To reduce test program development time, the software should be designed such that additional device sites (e.g., the number of devices on a single dual-independent bus (DIB)) can be added easily to the program. UWB's physical layer RF characteristics present several new challenges for semiconductor test. Plus, the forecasted market adoption could result in an unprecedented time-to-volume curve for operational planning and test engineering organizations. With careful test strategy consideration, semiconductor companies can achieve product quality and cost aspirations for this new product segment. Consider developing a test strategy that enables the flexibility to adjust fault coverage and maximize confidence in the quality of the product, while also reducing the cost of test through efficient multisite testing. ABOUT THE AUTHOR
Kyle Klatka is a product manager at Teradyne where he is responsible for wireless broadband test products. He holds a B.S.E.E. and a B.S. in Economics from Georgia Tech.
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